SLVAEU8 July 2020 – MONTH TPS25831-Q1
The failure mode distribution estimation for TPS25831-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| SW no output | 25% |
| CSP and CSN/OUT not in specification – voltage or timing | 20% |
| LS_GD no output | 5% |
| LS_GD not in specification – voltage or timing | 5% |
| DP_IN, DM_IN – no output | 10% |
| DP_IN, DM_IN – not in specification – voltage or timing | 10% |
| CC1, CC2 no output | 5% |
| CC1, CC2 not in specification – voltage or timing | 10% |
| FAULT, POL, LD_DET, THERM_WARN false trip or fails to trip | 5% |
| Short circuit any two pins | 5% |
The FMD in Table 3-1 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.