Along with non-zero pulse-width distortion, finite output slew-rate is the other principal timing constraint that limits high side switch operating frequency and minimum input pulse-width. While this appears as a drawback when driving resistive and LED loads, reduced slew-rates are useful in limiting inrush current for large capacitive loads.

Taking the TPS1H100-Q1 HSS as an example, ON and OFF slew rate are nominally SR_ON = 0.36 V/μs and SR_OFF = 0.32 V/μs, and stable over operating conditions. This leads to rise and fall times being heavily dependent on (and directly proportional to) the supply voltage V_vs. If we consider the minimum slew rate specification from the TPS1H100-Q1 data sheet the slew rate will be as low as SR_ON,OFF = 0.1 V/μs. This range can drastically reduce the power delivered at higher operating frequencies and supply voltages if ignored.

We can estimate the rise and fall times from the ON/OFF slew rates as follows,

In extreme cases, unreasonably small input pulses can cause the HSS output to be unable to reach before dropping if the sum of output rise and fall times is less than the input pulse width. In LED applications where the output needs to exceed the forward voltage(s) of the LED string, such distorted output pulses will result in lower than expected light intensity or possibly no visible output.

Ensuring the output rise/fall times are at least an order of magnitude less the ON pulse duration means we can safely ignore the effects of slew rate on both power and output accuracy. This same general rule can also applied to propagation-delay mismatch effects. If this cannot be guaranteed, designers wishing to operate their systems at the highest PWM frequency possible must make deliberate effort to understand the effect of slow and mismatched rise times. In the remainder of this section, the impact of slew rate on the operation of the PWM will be analyzed in more detail, both from the perspective of timing and load power.