Table 5. Design Parameters

9.2.2.1 Input Capacitor (C_IN)

To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a discharged load capacitor or short-circuit, a capacitor needs to be placed between VIN and GND. A 1 µF ceramic capacitor, C_IN, placed close to the pins, is usually sufficient. Higher values of C_IN can be used to further reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.

9.2.2.2 Output Capacitor (C_L) (Optional)

Becuase of the integrated body diode in the MOSFET, a C_IN greater than C_L is highly recommended. A C_L greater than C_IN can cause V_OUT to exceed V_IN when the system supply is removed. This could result in current flow through the body diode from VOUT to VIN. A C_IN to C_L ratio of 10 to 1 is recommended for minimizing V_IN dip caused by inrush currents during startup.

9.2.2.3 Shutdown Sequencing During Unexpected System Power Loss

Microcontrollers and processors often have a specific shutdown sequence in which power needs to be removed. Using the adjustable Quick Output Discharge function of the TPS22918, adding a load switch to each power rail can be used to manage the power down sequencing in the event of an unexpected system power loss (i.e. battery removal). To determine the QOD values for each load switch, first confirm the power down order of the device you wish to power sequence. Be sure to check if there are voltage or timing margins that must be maintained during power down. Next, consult QOD Fall Time Table in the Quick Output Discharge (QOD) feature description to determine appropriate C_OUT and R_QOD values for each power rail's load switch so that the load switches' fall times correspond to the order in which they need to be powered down. In the above example, we would like this power rail's fall time to be 4 ms. Using Equation 2, to determine the appropriate R_QOD to achieve our desired fall time.
Because fall times are measured from 90% of V_OUT to 10% of V_OUT, the equation becomes:

Refer to Figure 7, R_PD at V_IN = 5 V is approximately 25 Ω. Using Equation 1, the required external QOD resistance can be calculated:

9.2.2.4 VIN to VOUT Voltage Drop

The VIN to VOUT voltage drop in the device is determined by the R_ON of the device and the load current. The R_ON of the device depends upon the VIN conditions of the device. Refer to the R_ON specification of the device in the Electrical Characteristics table of this data sheet. When the R_ON of the device is determined based upon the VIN conditions, use Equation 8 to calculate the VIN to VOUT voltage drop:

9.2.2.5 Inrush Current

Use Equation 9 to determine how much inrush current will be caused by the C_L capacitor:

Equation 9.

where

• I_INRUSH = amount of inrush caused by C_L
• C_L = capacitance on VOUT
• dt = Output Voltage rise time during the ramp up of VOUT when the device is enabled
• dV_OUT = change in V_OUT during the ramp up of VOUT when the device is enabled

The appropriate rise time can be calculated using the design requirements and the inrush current equation. As we are calculating the rise time (measured from 10% to 90% of V_OUT), we will account for this in our dV_OUT parameter (80% of V_OUT = 4 V).

To ensure an inrush current of less than 400 mA, choose a CT value that will yield a rise time of more than 220 μs. Consulting Table 2 at V_IN = 5 V, CT = 220 pF will provide a typical rise time of 650 μs. Inputting this rise time and voltage into Equation 9, yields:

This inrush current can be seen in the Application Curves section. An appropriate C_L value should be placed on VOUT such that the I_MAX and I_PLS specifications of the device are not violated.