SNAU260A October   2020  – February 2021 LMK5C33216

ADVANCE INFORMATION  

  1.   Trademarks
  2. 1Introduction
  3. 2EVM Quick Start
  4. 3EVM Configuration
    1. 3.1 Power Supply
    2. 3.2 Logic Inputs and Outputs
    3. 3.3 Switching Between I2C and SPI
    4. 3.4 Generating SYSREF Request
    5. 3.5 XO Input
      1. 3.5.1 38.88-MHz TCXO (Default)
      2. 3.5.2 External Clock Input
    6. 3.6 Reference Clock Inputs
    7. 3.7 Clock Outputs
    8. 3.8 Status Outputs and LEDS
    9. 3.9 Requirements for Making Measurements
  5. 4EVM Schematics
    1. 4.1 Power Supply Schematic
    2. 4.2 Power Distribution Schematic
    3. 4.3 LMK5C33216 and Input Reference Inputs IN0 to IN1 Schematic
    4. 4.4 Clock Outputs OUT0 to OUT3 Schematic
    5. 4.5 Clock Outputs OUT4 to OUT9 Schematic
    6. 4.6 Clock Outputs OUT10 to OUT15 Schematic
    7. 4.7 XO Schematic
    8. 4.8 Logic I/O Interfaces Schematic
    9. 4.9 USB2ANY Schematic
  6. 5EVM Bill of Materials
    1. 5.1 Loop Filter and Vibration Nonsensitive Capacitors
  7. 6Appendix A - TICS Pro LMK5C33216 Software
    1. 6.1 Using the Start Page
      1. 6.1.1 Step 1
      2. 6.1.2 Step 2
      3. 6.1.3 Step 3
      4. 6.1.4 Step 4
      5. 6.1.5 Step 5
      6. 6.1.6 Step 6
      7. 6.1.7 Step 7
    2. 6.2 Using the Status Page
    3. 6.3 Using the Input Page
      1. 6.3.1 Cascaded Configurations
        1. 6.3.1.1 Cascade VCO to APLL Reference
    4. 6.4 Using APLL1, 2, and 3 Pages
    5. 6.5 Using the DPLL1, 2, and 3 Pages
      1. 6.5.1 DPLL DCO
    6. 6.6 Using the Validation Page
    7. 6.7 Using the GPIO Page
    8. 6.8 Using the Outputs Page
  8. 7Revision History

3.1 Power Supply

The LMK5C33216 has VDD and VDDO supply pins that operate from 3.3 V ± 5%.

J1 is the main power terminal to the external power supply. Power SMA port VIN1 (J2) provides an alternative connector style to apply power through coax cable. By default this SMA connector is not populated.

On the EVM, the default power configuration uses the onboard LDO regulators to power all VDD and VDDO pins from an external 5-V supply input VIN1 to J1 (or J2). A Dual LDO regulator (U3) is used to power the VDD and VDDO rails of the DUT and its peripheral circuitry. A separate LDO regulator (U4),also supplied from VIN1, is used to power the onboard XO circuits.

Note: Not every power connection is used or required to operate the EVM. Other power configurations are possible. See the power schematics in Figure 4-1 and Figure 4-2.
GUID-20201014-CA0I-D3HF-0SBW-LR8HQDXXHLW8-low.png Figure 3-2 Default Power Jumper Configuration

Figure 3-2 shows the default power jumper locations and settings. Table 3-2 shows the suggested power configurations for the DUT.

Table 3-2 Suggested Power Configurations
CONNECTION NAME ONBOARD LDO REGULATORS
(DEFAULT)		 DIRECT EXTERNAL SUPPLIES
VD = 3.3 V (LDO1)
VDDO = 3.3 V (LDO2)		 VDD = 3.3 V (EXT. VIN1)
VDDO = 3.3 V (EXT. VIN2)
J1 PWR Pin 1 (VIN1): Connect to external 5-V supply
Pin 2 (VIN2): n/a
Pin 3 (VIN3): n/a
Pin 4 (GND): Connect to supply ground		 Pin 1 (VIN1): Connect to external 3.3-V supply
Pin 2 (VIN2): Connect to external 3.3-V supply Pin 3 (VIN3): n/a
Pin 4 (GND): Connect to supply ground
JP1 VDD Tie pins 1-2 (adjacent to designator) to select 3.3 V from LDO1 to VDD Plane Tie pins 2-3 (opposite to designator) to select external VIN1 to VDD Plane
JP2 VDDO Tie pins 1-2 (adjacent to designator) to select 3.3 V from LDO2 to VDDO Plane Tie pins 2-3 (opposite to designator) to select external VIN2 to VDDO Plane
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