SNLA340 October 2022 DP83TC811R-Q1 , DP83TC811S-Q1 , DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TC814R-Q1 , DP83TC814S-Q1 , DP83TG720R-Q1 , DP83TG720S-Q1
Strap features on RX_D0, RX_D1, RX_D2, LED_0, and LED_1 are same for all four devices. They can be used by keeping the strap resistors open or by using a pull up resistor. Test Mode straps are not supported on DP83TC812, DP83TC814, and DP83TG720. This allows those strap pins to be used as two level straps. The PHYs can be configured in Test Modes via register access.
When strap resistors are not used, the PHY's internal pull down resistors will configure the PHY in Mode 1 by default. However, for LED pins it is recommended to use pull down resistor in parallel with the an LED when using Mode 1.
| PIN NO. | PIN NAME | DP83TC811 | DP83TC812, DP83TC814, DP83TG720 | ||||
|---|---|---|---|---|---|---|---|
| STRAP MODE Table 2-7 | STRAP | STRAP MODE Table 2-8 | STRAP | ||||
| 26 | RX_D0 | MAC[0] | TEST[0] | MAC[0] | NA | ||
| Mode 1 | 0 | 0 | Mode 1 | 0 | |||
| Mode 2 | 0 | 1 | NA | NA | |||
| Mode 3 | 1 | 0 | NA | NA | |||
| Mode 4 | 1 | 1 | Mode 2 | 1 | |||
| 25 | RX_D1 | MAC[1] | TEST[1] | MAC[1] | NA | ||
| Mode 1 | 0 | 0 | Mode 1 | 0 | |||
| Mode 2 | 0 | 1 | NA | NA | |||
| Mode 3 | 1 | 0 | NA | NA | |||
| Mode 4 | 1 | 1 | Mode 2 | 1 | |||
| 24 | RX_D2 | MAC[2] | TEST[2] | MAC[2] | NA | ||
| Mode 1 | 0 | 0 | Mode 1 | 0 | |||
| Mode 2 | 0 | 1 | NA | NA | |||
| Mode 3 | 1 | 0 | NA | NA | |||
| Mode 4 | 1 | 1 | Mode 2 | 1 | |||
| 35 | LED_0 | MS | RESERVED | MS | NA | ||
| Mode 1 | 0 | Mode 1 | 0 | ||||
| Mode 2 | RESERVED | RESERVED | NA | NA | |||
| Mode 3 | RESERVED | RESERVED | NA | NA | |||
| Mode 4 | 1 | Mode 2 | 1 | ||||
| 6 | LED_1 | AUTO | RESERVED | AUTO | RESERVED | ||
| Mode 1 | 0 | Mode 1 | 0 | ||||
| Mode 2 | RESERVED | RESERVED | NA | NA | |||
| Mode 3 | RESERVED | RESERVED | NA | NA | |||
| Mode 4 | 1 | Mode 2 | 1 | ||||
Table 2-7 shows strap resistor values for DP83TC811 and Table 2-8 shows strap resistor values for DP83TC812, DP83TC814, and DP83TG720.
| MODE | IDEAL RH (kΩ) | IDEAL RL (kΩ) |
|---|---|---|
| 1 | OPEN | OPEN |
| 2 | 10 | 2.49 |
| 3 | 5.76 | 2.49 |
| 4 | 2.49 | OPEN |
| MODE | IDEAL RH (kΩ) |
|---|---|
| 1 | OPEN |
| 2 | 2.49 |
|
MS |
DESCRIPTION |
|---|---|
0 | 100BASE-T1 Slave Configuration |
1 | 100BASE-T1 Master Configuration |
|
MAC[2] |
MAC[1] |
MAC[0] |
DESCRIPTION |
|---|---|---|---|
0 | 0 | 0 | SGMII (4-wire) |
0 | 0 | 1 | MII (DP83TC81x only) |
0 | 1 | 0 | RMII Slave (DP83TC81x only) |
0 | 1 | 1 | RMII Master (DP83TC81x only) |
1 | 0 | 0 | RGMII (Align Mode) |
1 | 0 | 1 | RGMII (TX Internal Delay Mode) |
1 | 1 | 0 | RGMII (TX and RX Internal Delay Mode) |
1 | 1 | 1 | RGMII (RX Internal Delay Mode) |
|
TEST[2] |
TEST[1] |
TEST[0] |
DESCRIPTION |
|---|---|---|---|
0 | 0 | 0 | Normal Operation |
0 | 0 | 1 | Test Mode 1 |
0 | 1 | 0 | Test Mode 2 |
0 | 1 | 1 | RESERVED |
1 | 0 | 0 | Test Mode 4 |
1 | 0 | 1 | Test Mode 5 |
1 | 1 | 0 | RESERVED |
1 | 1 | 1 | RESERVED |
|
AUTO |
DESCRIPTION |
|---|---|
0 | Autonomous Mode, PHY able to establish link after power-up |
1 | Managed Mode, PHY must be allowed to establish link after power-up based on register write |