SNLA404 December   2022 DP83TC811R-Q1 , DP83TC811S-Q1 , DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TG720R-Q1 , DP83TG720S-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2PHY Link-up Sequence
    1. 2.1 Microcontroller Initialization
    2. 2.2 Power-up Sequence
      1. 2.2.1 All Supplies Ramped
      2. 2.2.2 PHY Clock Required Good
      3. 2.2.3 SMI Access Available
      4. 2.2.4 PHY Bootstraps Sampled
    3. 2.3 Check Device ID
    4. 2.4 PHY Initialization
      1. 2.4.1 Managed or Autonomous Mode?
      2. 2.4.2 Program PHY Configuration Settings, Enable Link Start-up
      3. 2.4.3 Program PHY Into Autonomous Mode
      4. 2.4.4 Soft Restart or Polling for Link
      5. 2.4.5 Results of Link Polling
    5. 2.5 Post Start-up Operation
    6. 2.6 Reset Sequence
      1. 2.6.1 Reset Initiated
      2. 2.6.2 SMI Access Available
      3. 2.6.3 Transition to Normal Operation
  5. 3Summary
  6.   A Appendix

1 Introduction

Ethernet PHYs have their own timing requirements as dictated in their respective data sheets. It is important that these requirements are met from a power supply standpoint to be able to supply the PHY appropriately as well as from a microcontroller standpoint to know exactly when a PHY is available for normal communication as well as register access for any programming needs for the system. Also, each PHY has an optimized register configuration which is loaded after the power-up sequence is complete.

Even after the PHY is configured and linked-up with the remote link partner, systems can choose to continue with status or health checks of the link using various PHY registers. Details of the required sequence to control and poll the PHY is described in this document.
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