SNLA404 December 2022 DP83TC811R-Q1 , DP83TC811S-Q1 , DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TG720R-Q1 , DP83TG720S-Q1
The PHY is sent into the reset state. This can be done in two ways, via hardware where the Reset pin is held low for F duration, or via software where register 0x1F[15] = ‘1’. The point in time when either the Reset pin is released, or the write command has been delivered to the PHY is known as T1. While these procedures do initiate a reset of the PHY, issuing the reset via pin toggling causes the PHY to sample the bootstraps while issuing a via register write does not cause resampling.
811 |
720 |
812 |
|
---|---|---|---|
Reset pin held low to initiate (µs) |
1 |
65 |
0.72 |