米6体育平台手机版

SNVU663A June 2019 – May 2021 LP87524-Q1 , LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

3.1.1 LP87524B-Q1 OTP Configuration

Table 3-2 BUCK0, BUCK1, BUCK2, BUCK3 OTP Settings

	Description	Bit Name	LP87524B-Q1	Configurable
General settings	Buck phase configuration (e.g. four single phase denoted as 1+1+1+1, four phase single output denoted as 4 ph).	N/A	1+1+1+1	No
	Switching frequency	N/A	4 MHz	No
	Spread spectrum	EN_SPREAD_SPEC	No	Yes
	Startup and shutdown delay range, 0...4.8 ms / 0... 9.6 ms / 0...15 ms / 0...30 ms	DOUBLE_DELAY, HALF_DELAY	0...15 ms	Yes
BUCK0	Output voltage	BUCK0_VSET	3300 mV	Yes
	Enable, ENx-pin or I²C register	EN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECT	I²C and EN1	Yes
	Force PWM mode or auto mode	BUCK0_FPWM	auto	Yes
	Force multiphase mode or auto mode	BUCK0_FPWM_MP	auto	Yes
	Peak current limit	ILIM0	2.5 A	Yes
	Slew rate	SLEW_RATE0	3.8 mV/µs	Yes
	Startup Delay	BUCK0_STARTUP_DELAY	5 ms	Yes
	Shutdown Delay	BUCK0_SHUTDOWN_DELAY	0 ms	Yes
BUCK1	Output voltage	BUCK1_VSET	1200 mV	Yes
	Enable, EN-pin or I²C register	EN_BUCK1, EN_PIN_CTRL1, BUCK1_EN_PIN_SELECT	I²C and EN1	Yes
	Force PWM mode or auto mode	BUCK1_FPWM	auto	Yes
	Peak current limit	ILIM1	2.5 A	Yes
	Slew rate	SLEW_RATE1	3.8 mV/µs	Yes
	Startup Delay	BUCK1_STARTUP_DELAY	5 ms	Yes
	Shutdown Delay	BUCK1_SHUTDOWN_DELAY	0 ms	Yes
BUCK2	Output voltage	BUCK2_VSET	1800 mV	Yes
	Enable, ENx-pin or I²C register	EN_BUCK2, EN_PIN_CTRL2, BUCK2_EN_PIN_SELECT	I²C and EN1	Yes
	Force PWM mode or auto mode	BUCK2_FPWM	Force PWM	Yes
	Force multiphase mode or auto mode	BUCK2_FPWM_MP	auto	Yes
	Peak current limit	ILIM2	5 A	Yes
	Slew rate	SLEW_RATE2	3.8 mV/µs	Yes
	Startup Delay	BUCK2_STARTUP_DELAY	2 ms	Yes
	Shutdown Delay	BUCK2_SHUTDOWN_DELAY	0 ms	Yes
BUCK3	Output voltage	BUCK3_VSET	2300 mV	Yes
	Enable, EN-pin or I²C register	EN_BUCK3, EN_PIN_CTRL3, BUCK3_EN_PIN_SELECT	I²C and EN1	Yes
	Force PWM mode or auto mode	BUCK3_FPWM	Force PWM	Yes
	Peak current limit	ILIM3	3.5 A	Yes
	Slew rate	SLEW_RATE3	3.8 mV/µs	Yes
	Startup Delay	BUCK3_STARTUP_DELAY	0 ms	Yes
	Shutdown Delay	BUCK3_SHUTDOWN_DELAY	1 ms	Yes

Table 3-3 lists the device settings for GPIOs.

Table 3-3 EN, CLKIN and GPIO Pin Settings

	Description	Bit Name	LP87524B-Q1	Configurable
EN1 (GPIO1) pin	EN1 (GPIO1) pin pulldown resistor enable or disable	EN1_PD	Enabled	Yes
EN2 (GPIO2) pin	EN2 (GPIO2) pin pulldown resistor enable or disable	EN2_PD	Disabled	Yes
EN3 (GPIO3) pin	EN3 (GPIO3) pin pulldown resistor enable or disable	EN3_PD	Disabled	Yes
CLKIN pin	CLKIN pin pull-down resistor enable or disable	CLKIN_PD	Enabled	Yes
	Frequency of external clock when connected to CLKIN	EXT_CLK_FREQ	2 MHz	Yes
	Mode for the internal PLL. When PLL disabled, internal RC OSC is used	PLL_MODE[1:0]	Enabled	Yes
EN1 (GPIO) control	Enable or GPIO	GPIO1_SEL	Enable	Yes
	Input or output in GPIO mode	GPIO1_DIR	Input	Yes
	Output type open drain or push-pull	GPIO1_OD	Push-pull	Yes
EN2 (GPIO) control	Enable or GPIO	GPIO2_SEL	GPIO	Yes
	Input or output in GPIO mode	GPIO2_DIR	Output	Yes
	Output type open drain or push-pull	GPIO2_OD	Open drain	Yes
	Pin control of GPIO, EN1 or EN3	EN_PIN_CTRL_GPIO2, EN_PIN_SELECT_GPIO2	EN1	Yes
	Startup Delay	GPIO2_STARTUP_DELAY	5 ms	Yes
	Shutdown Delay	GPIO2_SHUTDOWN_DELAY	0 ms	Yes
EN3 (GPIO) control	Enable or GPIO	GPIO3_SEL	GPIO	Yes
	Input or output in GPIO mode	GPIO3_DIR	Output	Yes
	Output type open drain or push-pull	GPIO3_OD	Open drain	Yes
	Pin control of GPIO, EN1 or EN2	EN_PIN_CTRL_GPIO3, EN_PIN_SELECT_GPIO3	EN1	Yes
	Startup Delay	GPIO3_ STARTUP_ DELAY	3 ms	Yes
	Shutdown Delay	GPIO3_ SHUTDOWN_ DELAY	0 ms	Yes

Table 3-4 shows device settings for PGOOD.

Table 3-4 PGOOD OTP Settings

	Description	Bit Name	LP87524B-Q1	Configurable
Signals monitored by PGOOD	BUCKx output voltage / voltage and current (master bucks)	PGx_SEL	Voltage	Yes
PGOOD mode selections	PGOOD thresholds for BUCKx (Undervoltage / Window (undervoltage and overvoltage))	PGOOD_WINDOW	Window	Yes
	PGOOD valid debounce time	PGOOD_SET_DELAY	11 ms	Yes
	PGOOD signal mode (status / latched until fault source read)	EN_PGFLT_STAT	Status	Yes
	PGOOD output mode (push-pull or open drain)	PGOOD_OD	Open drain	Yes
	PGOOD polarity (active high / active low)	PGOOD_POL	Active high (power valid)	Yes

Table 3-5 lists the device settings for thermal warning. Also refer to Table 3-7 for interrupt settings.

Table 3-5 Protections OTP Settings

	Description	Bit Name	LP87524B-Q1	Configurable
Protections	Thermal warning level (125°C or 137°C)	TDIE_WARN_LEVEL	137°C	Yes
Protections	Input over-voltage protection	N/A	Enabled	No

Table 3-6 shows device settings for I²C and OTP revision ID values.

Table 3-6 Device Identification and I²C Settings

	Description	Bit Name	LP87524B-Q1	Configurable
I²C slave ID (7-bit)	Slave address	N/A	0x60	No

Table 3-7 lists device settings for interrupts. When interrupt from an event is unmasked, an interrupt is generated to nINT pin.

Table 3-7 Interrupt Mask Settings

	Interrupt event	Bit Name	LP87524B-Q1	Configurable
General	Sync clock appears or disappears	SYNC_CLK_MASK	Unmasked	Yes
	Thermal warning	TDIE_WARN_MASK	Unmasked	Yes
	Load measurement ready	I_LOAD_READY_MASK	Masked	Yes
	Register reset	RESET_REG_MASK	Masked	Yes
BUCK0	Buck0 PGOOD has reached threshold level	BUCK0_PG_MASK	Masked	Yes
BUCK0	Buck0 current limit triggered	BUCK0_ILIM_MASK	Masked	Yes
BUCK1	Buck1 PGOOD has reached threshold level	BUCK1_PG_MASK	Masked	Yes
BUCK1	Buck1 current limit triggered	BUCK1_ILIM_MASK	Masked	Yes
BUCK2	Buck2 PGOOD has reached threshold level	BUCK2_PG_MASK	Masked	Yes
BUCK2	Buck2 current limit triggered	BUCK2_ILIM_MASK	Masked	Yes
BUCK3	Buck3 PGOOD has reached threshold level	BUCK3_PG_MASK	Masked	Yes
BUCK3	Buck3 current limit triggered	BUCK3_ILIM_MASK	Masked	Yes