The general methodology for evaluating signal integrity for high-speed SERDES interfaces is illustrated in Figure 1-1. This involves running a channel simulation for the serial link. The methodology uses IBIS-Algorithmic Modeling Interface (AMI) models for the Tx/Rx blocks. The basic setup and settings documented here can be used to validate all SerDes links and also across a variety of EDA Signal Integrity simulators. This channel simulation should be performed as a signoff check for all high-speed Serial Link interfaces.

Figure 1-1 Signal Integrity Analysis Setup - Channel Simulation