SPRZ408D June 2014 – June 2021 AM4372 , AM4376 , AM4377 , AM4378 , AM4379
Advisories are numbered in the order in which they were added to this document. Some advisory numbers may be moved to the next revision and others may have been removed because the design exception was fixed or documented in the device-specific data manual or peripheral user's guide. When items are moved or deleted, the remaining numbers remain the same and are not re-sequenced.
| NUMBER | TITLE | SILICON REVISION AFFECTED | |
|---|---|---|---|
| 1.1 | 1.2 | ||
| Section 3.1.1 | LPDDR2/DDR3: JEDEC Compliance for Minimum Self-Refresh Command Interval | X | X |
| Section 3.1.2 | DDR3/DDR3L: JEDEC Specification Violation for DDR3 RESET Signal When Implementing RTC+DDR Mode | X | X |
| NUMBER | TITLE | SILICON REVISION AFFECTED | |
|---|---|---|---|
| 1.1 | 1.2 | ||
| Advisory 1 | UART: Extra Assertion of FIFO Transmit DMA Request, UARTi_DMA_TX | X | X |
| Advisory 2 | ROM: USB Host Boot is Unsupported | X | |
| Advisory 3 | ROM: USB Client Boot is Unsupported | X | |
| Advisory 4 | ROM: RGMII Clocking Register is Not Configured Properly at OPP50 | X | |
| Advisory 5 | ROM: Trace Vector Does Not Reflect that TFTP Transfer Has Been Initiated | X | |
| Advisory 6 | ROM: Booting from Redundant Image in NAND Does Not Work as Expected | X | |
| Advisory 7 | ROM: NAND Booting is Slower than Expected | X | |
| Advisory 8 | ROM: In NOR Low Latency Boot Mode, Wait Monitoring Will Not Work | X | |
| Advisory 9 | ROM: NAND ECC May Not Be Chosen Correctly by the ROM | X | |
| Advisory 10 | ROM: Peripheral Boot is Not Supported | X | |
| Advisory 11 | Asynchronous Bridge Corruption | X | X |
| Advisory 12 | DebugSS: Register Identifier Field (MasterID) of Statistics Collector Has a Default Value of 0x0 Instead of the Expected ID | X | X |
| Advisory 13 | DSS: DSS Smart Standby May Cause Synchronization Issues | X | X |
| Advisory 14 | DSS: DSS Limitations | X | X |
| Advisory 15 | ROM: NAND Boot Mode is Unsupported | X | |
| Advisory 16 | McASP: McASP to EDMA Synchronization Level Event Can Be Lost | X | X |
| Advisory 17 | DebugSS: DebugSS Does Not Acknowledge Idle Request | X | X |
| Advisory 19 | TSC_ADC: False Pen-up Interrupts | X | X |
| Advisory 20 | GPTimer: Delay Needed to Read Some GPTimer Registers After Wakeup | X | X |
| Advisory 21 | UART: UART0-5 Do Not Acknowledge Idle Request After DMA Has Been Enabled | X | X |
| Advisory 22 | Watchdog Timers: Delay Needed to Read Some WDTimer Registers After Wakeup | X | X |
| Advisory 24 | VDD_MPU_MON Not Connected to Die | X | X |
| Advisory 25 | Ethernet Boot: ROM May Select 1-Gbit, Half-Duplex Mode During Auto-negotiation and Fail to Boot | X | X |
| Advisory 26 | AutoCMD12 Mode: CMD12 Command is Not Issued on Write Transfer Completion | X | X |
| Advisory 27 | UART: Spurious UART Interrupts When Using EDMA | X | X |
| Advisory 28 | UART: Transactions to MDR1 Register May Cause Undesired Effect on UART Operation | X | X |
| i2223 | ROM: Non-muxed Fast NOR boot does not onfigure A26 and A27 | X | X |
| i2224 | DCAN: RAMINIT_DONE intermittently fails to latch completion | X | X |
| i912 | QSPI: QSPI register bitfield incorrectly masked when read | X | X |
| i2225 | Possible underflow condition when using EDMA with UART1, UART2, and UART3 | X | X |
| i2226 | PRU-ICSS: Burst data transfer between ICSS instances not supported | X | X |