SPRZ544A March 2023 – December 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1
Usage Notes Matrix lists all usage notes and the applicable silicon revision(s). Advisories Matrix lists all advisories, modules affected, and the applicable silicon revision(s).
| ID | DESCRIPTION | SILICON REVISIONS AFFECTED |
|---|---|---|
| AM62Ax 1.0 | ||
| Boot | i2372 — ROM doesn't support select multi-plane addressing schemes in Serial NAND boot | YES |
| OSPI | i2351 — OSPI: Controller does not support Continuous Read mode with NAND Flash | YES |
| MODULE | DESCRIPTION | SILICON REVISIONS AFFECTED |
|---|---|---|
| AM62Ax 1.0 | ||
| Boot | i2366— Boot: ROM does not comprehend specific JEDEC SFDP features for 8D-8D-8D operation | YES |
| Boot | i2371— Boot: ROM code may hang in UART boot mode during data transfer | YES |
| Boot | i2410— Boot: ROM may fail to boot due to i2409 | YES |
| c71x | i2199 — C71x: SE returning incorrect data when non-aligned transposed stream crosses AM1 circular buffer boundary | YES |
| C7x | i2120 — C71x: SE returning incorrect data when non-aligned transposed stream crosses AM1 circular buffer boundary | YES |
| CSI_RX | i2190 — CSI_RX_IF may enter unknown state following an incomplete frame | YES |
| CPSW | i2208 — CPSW: ALE IET Express Packet Drops | YES |
| CPSW | i2401 — CPSW: Host Timestamps Cause CPSW Port to Lock up | YES |
| DSS | i2097 — DSS: Disabling a layer connected to Overlay may result in synclost during the next frame | YES |
| ECC_AGGR | i2049 — ECC_AGGR: Potential IP Clockstop/Reset Sequence Hang due to Pending ECC Aggregator Interrupts | YES |
| Interrupt Aggregator | i2196 — IA: Potential deadlock scenarios in IA | YES |
| MCAN | i2278 — MCAN: Message Transmit order not guaranteed from dedicated Tx Buffers configured with same Message ID | YES |
| MCAN | i2279 — MCAN: Specification Update for dedicated Tx Buffers and Tx Queues configured with same Message ID | YES |
| MMCHS | i2312 — MMCHS HS200 and SDR104 Command Timeout Window Too Small | YES |
| OSPI | i2189 — OSPI: Controller PHY Tuning Algorithm | YES |
| OSPI | i2249 — OSPI: Failing OSPI DDR PHY Internal Pad Loopback and No Loopback timing modes | YES |
| OSPI | i2383 — OSPI: 2-byte address is not supported in PHY DDR mode | YES |
| PRG | i2253 —PRG: CTRL_MMR STAT registers are unreliable indicators of POK threshold failure | YES |
| PSIL | i2137 — PSIL: Clock stop operation can result in undefined behavior | YES |
| RAT | i2062 — RAT: Error Interrupt Triggered Even When Error Logging Disable Is Set | YES |
| RESET | i2407— RESET: MCU_RESETSTATz unreliable when MCU_RESETz is asserted low | YES |
| USART | i2310 — USART: Erroneous triggering of timeout interrupt | YES |
| USART | i2311 — USART Spurious DMA Interrupts | YES |
| USB | i2134 — USB: 2.0 Compliance Receive Sensitivity Test Limitation | YES |
| USB | i2409 — USB: USB2 PHY locks up due to short suspend | YES |
| VPU | i2373 — VPU: VPU's interrupt is not routed to A53 | YES |