ZHCAEJ8 October 2024 TAC5412-Q1
单稳态模式下的 SG2 会生成具有定义的延音时间间隔的单个脉冲。请参阅节 3.2。要再次启动脉冲,用户必须按原样执行整个脚本。该模式大多需要延音计时器配置。
单稳态模式下没有重启时间配置。表 3-4 中介绍了适用于此模式的其他 ADSR 参数。
Key: w a0 XX YY ==> write to I2C address 0xa0, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
#The following list gives an example sequence of items that must be #executed in the time between powering the device up and reading data #from the device. Note that there are other valid sequences depending #on which features are used.
#See the corresponding EVM user guide for jumper settings and audio #connections.
#
# Line-Out Fully-Differential 2-channel : OUT1P_M- Ch1, OUT2P_M- Ch2.
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 12.288 MHz (BCLK/FSYNC = 256) ###################################################################
#one shot mode
#repeat script to generate pulse again
w a0 01 01 # device reset
w a0 00 00 # locate page 0x00
w a0 02 09 # come out of sleep mode
# with VREF and DREG up
w a0 00 01 # locate page 0x01
w a0 2d 04 # enable the chirp only
w a0 00 17 # locate page 0x17
w a0 7c 02 18 2a 47 # chirp start frequency, 1khz
w a0 00 18 #locate page 0x18
w a0 08 00 35 9d d3 # chirp delta frequency of 100 Hz
w a0 08 00 00 00 00 # chirp delta frequency is set to zero
w a0 00 1c #locate page 0x1c
w a0 40 ff ff ff ff # adsr_note; write this code to generate a chirp
#and initiate the signal again with 0x01,
#the signal will last based on the sustain timer set
#restart
w a0 50 ff ff ff ff # restart_timer
#sustain
#w a0 54 00 00 5d c0 #24000 samples at 500ms
w a0 54 00 00 12 c0 # 480 samples 100ms default
w a0 00 17 # locate page 0x17
w a0 74 FF FF FF FF # power up delay continued
w a0 00 11 # locate page 0x11
w a0 70 3F FF 3F FF # Please refer the table to set volumes #accordingly
w a0 74 0F FF 0F FF # Please refer the table to set volumes #accordingly
w a0 00 00 # locate page 0x00
w a0 76 0c # enable 2 DAC channels
w a0 78 40 # enable DAC
w a0 40 00 00 00 01 #adsr enable note.