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7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	HVDD to AGND	–0.3	18	V
	HVSS to AGND	–18	0.3
	AVDD to AGND	–0.3	6
	DVDD to DGND	–0.3	6
Analog input voltage		HVSS – 0.3	HVDD + 0.3	V
Reference input voltage with respect to AGND		AGND – 0.3	AVDD + 0.3	V
Digital input voltage with respect to DGND		DGND – 0.3	DVDD + 0.3	V
Ground voltage difference AGND to DGND			±0.3	V
Input current to all pins except supply			±10	mA
Maximum virtual junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
AVDD	Analog supply voltage	4.5	5.0	5.5	V
DVDD	Buffer I/O supply voltage	2.7	3.3	5.5	V
HVDD	Input positive supply voltage	5.0	15.0	16.5	V
HVSS	Input negative supply voltage	–16.5	–15.0	–5.0	V
T_A	Operating ambient temperature range	–40	25	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS85x8		UNIT
		RGC (VQFN)	PM (LQFP)
		64 PINS	64 PINS
R_θJA	Junction-to-ambient thermal resistance	22	48.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	9.0	9.4	°C/W
R_θJB	Junction-to-board thermal resistance	3.6	21.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	2.9	21.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.3	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: General

All minimum and maximum specifications are at T_A = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (internal), V_IN = ±10 V, and f_DATA = max, unless otherwise noted. Typical values are at T_A = 25°C, HVDD = 15 V, HVSS = –15 V, AVDD = 5 V, and DVDD = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
CHXX	Bipolar full-scale range	RANGE pin, RANGE bit = 0	–4 VREF		4 VREF	V
CHXX	Bipolar full-scale range	RANGE pin, RANGE bit = 1	–2 VREF		2 VREF	V
	Input capacitance	Input range = ±4 VREF		10		pF
	Input capacitance	Input range = ±2 VREF		20		pF
	Input leakage current	No ongoing conversion	–1		1	μA
	Aperture delay			5		ns
	Aperture delay matching	Common CONVST for all channels		100		ps
	Aperture jitter			50		ps
PSRR	Power-supply rejection ratio	At output code FFFFh, related to HVDD and HVSS		–78		dB
REFERENCE VOLTAGE OUTPUT (REF_OUT)
VREF	Reference voltage	2.5-V operation, REFDAC = 3FFh	2.485	2.5	2.515	V
		2.5-V operation, REFDAC = 3FFh at 25°C	2.496	2.5	2.504
		3.0-V operation, REFDAC = 3FFh	2.985	3.0	3.015
		3.0-V operation, REFDAC = 3FFh at 25°C	2.995	3.0	3.005
dVREF/dT	Reference voltage drift			±10		ppm/°C
PSRR	Power-supply rejection ratio	At output code FFFFh, related to AVDD		–77		dB
IREF_OUT	Output current	At dc current	–2		2	mA
I_REFSC	Short-circuit current⁽¹⁾			50		mA
t_REFON	Turn-on settling time			10		ms
	External load capacitance	At REF_xP, REF_xN pins	4.7	10		μF
	External load capacitance	At REFIO pin	100	470		nF
REFDAC	Tuning range	Internal reference output voltage range	0.2 VREF		VREF	V
	REFDAC resolution		10			Bits
DNL_DAC	REFDAC differential nonlinearity		–1	±0.1	1	LSB
INL_DAC	REFDAC integral nonlinearity		–2	±0.1	2	LSB
V_OSDAC	REFDAC offset error	VREF = 0.5 V (DAC = 0CDh)	–4	±0.65	4	LSB
REFERENCE VOLTAGE INPUT (REF_IN)
VREF_IN	Reference input voltage		0.5	2.5	3.025	V
	Input resistance			100		MΩ
	Input capacitance			5		pF
	Reference input current				1	μA
DIGITAL INPUTS⁽²⁾ (CMOS with Schmitt-Trigger Logic Family)
	High-level input voltage		0.7 DVDD		DVDD + 0.3	V
	Low-level input voltage		DGND – 0.3		0.3 DVDD	V
	Input current	V_I = DVDD to DGND	–50		50	nA
	Input capacitance			5		pF
DIGITAL OUTPUTS⁽²⁾
	Output capacitance			5		pF
	Load capacitance				30	pF
	High-impedance-state output current		–50		50	nA
	Logic family			CMOS
V_OH	High-level output voltage	I_OH = 100 μA	DVDD – 0.6			V
V_OL	Low-level output voltage	I_OH = –100 μA			DGND + 0.4	V
POWER-SUPPLY REQUIREMENTS
AVDD	Analog supply voltage		4.5	5.0	5.5	V
DVDD	Buffer I/O supply voltage		2.7	3.3	5.5	V
HVDD	Input positive supply voltage		5.0	15.0	16.5	V
HVSS	Input negative supply voltage		–16.5	–15.0	–5.0	V
IAVDD	Analog supply current	ADS8528, f_DATA = maximum		37.9	50.1	mA
		ADS8548, f_DATA = maximum		37.3	49.3
		ADS8568, f_DATA = maximum		36.6	48.4
		f_DATA = 250 kSPS, auto-sleep mode		20.3	30.0
		f_DATA = 200 kSPS, auto-sleep mode		17
		f_DATA = 10 kSPS, normal operation		30
		f_DATA = 10 kSPS, auto-sleep mode		4.6
		Auto-sleep mode, no ongoing conversion, internal conversion clock			7.0
		Power-down mode			0.03
IDVDD	Buffer I/O supply current	f_DATA = maximum		0.5	2.0	mA
		f_DATA = 250 kSPS		0.5	1.4
		f_DATA = 200 kSPS		0.5
		f_DATA = 10 kSPS		0.4
		Auto-sleep mode, no ongoing conversion, internal conversion clock			0.35
		Power-down mode			0.01
IHVDD	Input positive supply current	ADS8528, f_DATA = maximum		3.0	4.2	mA
		ADS8548, f_DATA = maximum		2.8	3.9
		ADS8568, f_DATA = maximum		2.3	3.2
		f_DATA = 250 kSPS		1.8	2.4
		f_DATA = 200 kSPS		1.5
		f_DATA = 10 kSPS		0.4
		Auto-sleep mode, no ongoing conversion, internal conversion clock			0.45
		Power-down mode			0.01
POWER-SUPPLY REQUIREMENTS (continued)
IHVSS	Input negative supply current	ADS8528, f_DATA = maximum		3.4	4.5	mA
		ADS8548, f_DATA = maximum		3.3	4.4
		ADS8568, f_DATA = maximum		2.7	3.6
		f_DATA = 250 kSPS		2.1	2.6
		f_DATA = 200 kSPS		1.7
		f_DATA = 10 kSPS		0.4
		Auto-sleep mode, no ongoing conversion, internal conversion clock			0.35
		Power-down mode			0.01
	Power dissipation⁽³⁾	ADS8528, f_DATA = maximum		287.1	430.1	mW
		ADS8548, f_DATA = maximum		279.7	419.1
		ADS8568, f_DATA = maximum		259.7	389.4
		f_DATA = 250 kSPS, auto-sleep mode		161.7	255.2
		f_DATA = 200 kSPS, auto-sleep mode		151.2
		f_DATA = 10 kSPS, normal operation		163.3
		f_DATA = 10 kSPS, auto-sleep mode		36.3
		Auto-sleep mode, no ongoing conversion, internal conversion clock			53.6
		Power-down mode			0.6

(1) Reference output current is not limited internally.

(2) Specified by design.

(3) Maximum power dissipation values are specified with HVDD = 15 V and HVSS = –15 V.

7.6 Electrical Characteristics: ADS8528

All minimum and maximum specifications are at T_A = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (internal), V_IN = ±10 V, and f_DATA = max, unless otherwise noted. Typical values are at T_A = 25°C, HVDD = 15 V, HVSS = –15 V, AVDD = 5 V, and DVDD = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SAMPLING DYNAMICS
	Conversion time	Internal conversion clock			1.33	μs
f_DATA	Throughput rate	Serial interface, all four SDOx active			480	kSPS
f_DATA	Throughput rate	Parallel interface			650	kSPS
DC ACCURACY
	Resolution			12		Bits
	No missing codes		12			Bits
INL	Integral linearity error⁽¹⁾		–0.75	±0.2	0.75	LSB
DNL	Differential linearity error		–0.5	±0.2	0.5	LSB
	Offset error		–1.5	±0.5	1.5	mV
	Offset error matching		–0.65		0.65	mV
	Offset error drift			±3.5		μV/°C
	Gain error	Referenced to voltage at REFIO	–0.5%	±0.25%	0.5%
	Gain error matching	Between channels of any pair	–0.2%		0.2%
	Gain error matching	Between any two channels	–0.4%		0.4%
	Gain error drift	Referenced to voltage at REFIO		±6		ppm/°C
AC ACCURACY
SNR	Signal-to-noise ratio	At f_IN = 10 kHz	73	73.9		dB
SINAD	Signal-to-noise ratio + distortion	At f_IN = 10 kHz	73	73.8		dB
THD	Total harmonic distortion⁽²⁾	At f_IN = 10 kHz		–89	–84	dB
SFDR	Spurious-free dynamic range	At f_IN = 10 kHz	84	92		dB
	Channel-to-channel isolation	At f_IN = 10 kHz		120		dB
BW	–3-dB small-signal bandwidth	In 4-VREF mode		48		MHz
BW	–3-dB small-signal bandwidth	In 2-VREF mode		24		MHz

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or percentage of the specified full-scale range.

(2) Calculated on the first nine harmonics of the input frequency.

7.7 Electrical Characteristics: ADS8548

All minimum and maximum specifications are at T_A = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (internal), V_IN = ±10 V, and f_DATA = max, unless otherwise noted. Typical values are at T_A = 25°C, HVDD = 15 V, HVSS = –15 V, AVDD = 5 V, and DVDD = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SAMPLING DYNAMICS
	Conversion time	Internal conversion clock			1.45	μs
f_DATA	Throughput rate	Serial interface, all four SDOx active			450	kSPS
f_DATA	Throughput rate	Parallel interface			600	kSPS
DC ACCURACY
	Resolution			14		Bits
	No missing codes		14			Bits
INL	Integral linearity error⁽¹⁾		–1	±0.5	1	LSB
DNL	Differential linearity error		–1	±0.25	1	LSB
	Offset error		–1.5	±0.5	1.5	mV
	Offset error matching		–0.65		0.65	mV
	Offset error drift			±3.5		μV/°C
	Gain error	Referenced to voltage at REFIO	–0.5%	±0.25%	0.5%
	Gain error matching	Between channels of any pair	–0.2%		0.2%
	Gain error matching	Between any two channels	–0.4%		0.4%
	Gain error drift	Referenced to voltage at REFIO		±6		ppm/°C
AC ACCURACY
SNR	Signal-to-noise ratio	At f_IN = 10 kHz	84	85		dB
SINAD	Signal-to-noise ratio + distortion	At f_IN = 10 kHz	83	84		dB
THD	Total harmonic distortion⁽²⁾	At f_IN = 10 kHz		–91	–86	dB
SFDR	Spurious-free dynamic range	At f_IN = 10 kHz	86	92		dB
	Channel-to-channel isolation	At f_IN = 10 kHz		120		dB
BW	–3-dB small-signal bandwidth	In 4-VREF mode		48		MHz
BW	–3-dB small-signal bandwidth	In 2-VREF mode		24		MHz

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or percentage of the specified full-scale range.

(2) Calculated on the first nine harmonics of the input frequency.

7.8 Electrical Characteristics: ADS8568

All minimum and maximum specifications are at T_A = –40°C to +125°C, specified supply voltage range, VREF = 2.5 V (internal), V_IN = ±10 V, and f_DATA = max, unless otherwise noted. Typical values are at T_A = 25°C, HVDD = 15 V, HVSS = –15 V, AVDD = 5 V, and DVDD = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SAMPLING DYNAMICS
	Conversion time	Internal conversion clock			1.7	μs
f_DATA	Throughput rate	Serial interface, all four SDOx active			400	kSPS
f_DATA	Throughput rate	Parallel interface			510	kSPS
DC ACCURACY
	Resolution			16		Bits
	No missing codes		16			Bits
INL	Integral linearity error⁽¹⁾	At T_A = –40°C to +85°C, VQFN package (RGC)	–3	±1.5	3	LSB
		At T_A = –40°C to +125°C, VQFN package (RGC)	–4	±1.5	4
		At T_A = –40°C to +85°C, LQFP package (PM)	–4	±1.5	4
		At T_A = –40°C to +125°C, LQFP package (PM)	–4.5	±1.5	4.5
DNL	Differential linearity error	At T_A = –40°C to +85°C	–1	±0.75	1.75	LSB
DNL	Differential linearity error	At T_A = –40°C to +125°C	–1	±0.75	2	LSB
	Offset error		–1.5	±0.5	1.5	mV
	Offset error matching		–0.65		0.65	mV
	Offset error drift			±3.5		μV/°C
	Gain error	Referenced to voltage at REFIO	–0.5%	±0.25%	0.5%
	Gain error matching	Between channels of any pair	–0.2%		0.2%
	Gain error matching	Between any two channels	–0.4%		0.4%
	Gain error drift	Referenced to voltage at REFIO		±6		ppm/°C
AC ACCURACY
SNR	Signal-to-noise ratio	At f_IN = 10 kHz, T_A = –40°C to +85°C	90	91.5		dB
SNR	Signal-to-noise ratio	At f_IN = 10 kHz, T_A = –40°C to +125°C	89	91.5		dB
SINAD	Signal-to-noise ratio + distortion	At f_IN = 10 kHz, T_A = –40°C to +85°C	87	90		dB
SINAD	Signal-to-noise ratio + distortion	At f_IN = 10 kHz, T_A = –40°C to +125°C	86.5	90		dB
THD	Total harmonic distortion⁽²⁾	At f_IN = 10 kHz, T_A = –40°C to +85°C		–94	–90	dB
THD	Total harmonic distortion⁽²⁾	At f_IN = 10 kHz, T_A = –40°C to +125°C		–94	–89.5	dB
SFDR	Spurious-free dynamic range	At f_IN = 10 kHz, T_A = –40°C to +85°C	90	95		dB
SFDR	Spurious-free dynamic range	At f_IN = 10 kHz, T_A = –40°C to +125°C	89.5	95		dB
	Channel-to-channel isolation	At f_IN = 10 kHz		120		dB
BW	–3-dB small-signal bandwidth	In 4-VREF mode		48		MHz
BW	–3-dB small-signal bandwidth	In 2-VREF mode		24		MHz

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or percentage of the specified full-scale range.

7.9 Serial Interface Timing Requirements

over recommended operating free-air temperature range (T_A), AVDD = 5 V, and DVDD = 2.7 V to 5.5 V (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
t_SCVX	CONVST_x high to XCLK rising edge setup time (CLKSEL = 1)		6		ns
t_XCLK	External conversion clock period	ADS8528	66.67		ns
		ADS8548	72.46
		ADS8568	85.11
	External conversion clock frequency	ADS8528	1	15.0	MHz
		ADS8548	1	13.8
		ADS8568	1	11.75
	External conversion clock duty cycle		40%	60%
t_CVL	CONVST_x low time		20		ns
t_ACQ	Acquisition time		280		ns
	Clock cycles per conversion	ADS85x8, t_CCLK or t_XCLK	19	20	Cycles
t_CONV	Conversion time	ADS8528, CLKSEL = 0		1.33	μs
		ADS8548, CLKSEL = 0		1.45
		ADS8568, CLKSEL = 0		1.7
t_DCVB	CONVST_x high to BUSY high delay			25	ns
t_BUFS	BUSY low to FS low time	ADS85x8, CLKSEL = 1	0		ns
		ADS8528, CLKSEL = 0⁽²⁾	67
		ADS8548, CLKSEL = 0⁽²⁾	73
		ADS8568, CLKSEL = 0⁽²⁾	86
t_FSCV	Bus access finished to next conversion start time	ADS8528	0		ns
		ADS8548	20
		ADS8568	40
t_SCLK	Serial clock period		0.022	10	μs
	Serial clock frequency		0.1	45	MHz
	Serial clock duty cycle		40%	60%
t_DMSB	FS low to MSB valid delay			12	ns
t_HDO	Output data to SCLK falling edge hold time		5		ns
t_PDDO	SCLK falling edge to new data valid propagation delay			17	ns
t_DTRI	FS high to SDO_x three-state delay			10	ns
t_SUDI	Input data to SCLK falling edge setup time		3		ns
t_HDI	Input data to SCLK falling edge hold time		5		ns

(1) All input signals are specified with t_R = t_F = 1.5 ns (10% to 90% of DVDD) and timed from a voltage level of (V_IL + V_IH) / 2.

(2) The device runs with an internal conversion clock. Data can be retrieved after the maximum conversion time t_CONV(max), independently from the BUSY signal. When referring the data readout to the falling edge of the BUSY signal, t_BUFS(min) must be taken into account (see the Data Readout and BUSY/INT Signal section).

7.10 Parallel Interface Timing Requirements (Read Access)

over recommended operating free-air temperature range (T_A), AVDD = 5 V, and DVDD = 2.7 V to 5.5 V (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
t_CVL	CONVST_x low time		20		ns
t_ACQ	Acquisition time		280		ns
	Clock cycles per conversion	ADS85x8, t_CCLK or t_XCLK	19	20	Cycles
t_CONV	Conversion time	ADS8528, CLKSEL = 0		1.33	µs
		ADS8548, CLKSEL = 0		1.45
		ADS8568, CLKSEL = 0		1.7
t_DCVB	CONVST_x high to BUSY high delay			25	ns
t_BUCS	BUSY low to CS low time	ADS85x8, CLKSEL = 1	0		ns
		ADS8528, CLKSEL = 0⁽³⁾	67
		ADS8548, CLKSEL = 0⁽³⁾	73
		ADS8568, CLKSEL = 0⁽³⁾	86
t_CSCV	Bus access finished to next conversion start time⁽²⁾	ADS8528	0		ns
		ADS8548	20
		ADS8568	40
t_CSRD	CS low to RD low time		0		ns
t_RDCS	RD high to CS high time		0		ns
t_RDL	RD pulse duration		20		ns
t_RDH	Minimum time between two read accesses		2		ns
t_PDDO	RD or CS falling edge to data valid propagation delay			15	ns
t_HDO	Output data to RD or CS rising edge hold time		5		ns
t_DTRI	CS high to DB[15:0] three-state delay			10	ns

(1) All input signals are specified with t_R = t_F = 1.5 ns (10% to 90% of DVDD) and timed from a voltage level of (V_IL + V_IH) / 2.

(2) See the CS signal or RD, whichever occurs first.

(3) The device runs with an internal conversion clock. Data can be retrieved after the maximum conversion time t_CONV(max), independently from the BUSY signal. When referring the data readout to the falling edge of the BUSY signal, t_BUCS(min) must be taken into account (see the Data Readout and BUSY/INT Signal section).

7.11 Parallel Interface Timing Requirements (Write Access)

over recommended ambient temperature range (T_A), AVDD = 5 V, and DVDD = 2.7 V to 5.5 V (unless otherwise noted)⁽¹⁾

		MIN	UNIT
t_CSWR	CS low to WR low time	0	ns
t_WRL	WR low pulse duration	15	ns
t_WRH	Minimum time between two write accesses	10	ns
t_WRCS	WR high to CS high time	0	ns
t_SUDI	Output data to WR rising edge setup time	5	ns
t_HDI	Data output to WR rising edge hold time	5	ns

(1) All input signals are specified with t_R = t_F = 1.5 ns (10% to 90% of DVDD) and timed from a voltage level of (V_IL + V_IH) / 2.

7.12 Typical Characteristics

graphs are valid for all devices of the family, at T_A = 25°C, HVDD = 15 V, HVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), V_IN = ±10 V, and f_DATA = maximum (unless otherwise noted)