8.3.1 Inside the INA826

See the Functional Block Diagram section for a simplified representation of the INA826. A more detailed diagram (shown in Figure 58) provides additional insight into the INA826 operation.

Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 8 mA.

The differential input voltage is buffered by Q₁ and Q₂ and is impressed across R_G, causing a signal current to flow through R_G, R₁, and R₂. The output difference amplifier, A₃, removes the common-mode component of the input signal and refers the output signal to the REF terminal.

The equations shown in Figure 58 describe the output voltages of A₁ and A₂. The V_BE and voltage drop across R₁ and R₂ produce output voltages on A₁ and A₂ that are approximately 0.8 V higher than the input voltages.

Figure 58. INA826 Simplified Circuit Diagram

8.3.2 Setting the Gain

Gain of the INA826 is set by a single external resistor, R_G, connected between pins 2 and 3. The value of R_G is selected according to Equation 1:

Equation 1.

Table 1 lists several commonly-used gains and resistor values. The 49.4-kΩ term in Equation 1 comes from the sum of the two internal 24.7-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift specifications of the INA826.

8.3.3 Offset Trimming

Most applications require no external offset adjustment; however, if necessary, adjustments can be made by applying a voltage to the REF terminal. Figure 59 shows an optional circuit for trimming the output offset voltage. The voltage applied to the REF terminal is summed at the output. The op amp buffer provides low impedance at the REF terminal to preserve good common-mode rejection.

Figure 59. Optional Trimming of the Output Offset Voltage

8.3.4 Input Common-Mode Range

The linear input voltage range of the INA826 input circuitry extends from the negative supply voltage to 1 V below the positive supply and maintains 84-dB (minimum) common-mode rejection throughout this range. The common-mode range for most common operating conditions is described in the input common-mode voltage versus output voltage Typical Characteristics curves (Figure 9 through Figure 15) and the offset voltage versus common-mode voltage curves (Figure 41 through Figure 43). The INA826 can operate over a wide range of power supplies and V_REF configurations, thus providing a comprehensive guide to common-mode range limits for all possible conditions is impractical.

The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A₁ and A₂, which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A₁ and A₂ (see Figure 58) provides a check for the most common overload conditions. The designs of A₁ and A₂ are identical and the outputs can swing to within approximately 100 mV of the power-supply rails. For example, when the A₂ output is saturated, A₁ can still be in linear operation, responding to changes in the noninverting input voltage. This difference can give the appearance of linear operation but the output voltage is invalid.

A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode range that extends to single-supply ground, the INA826 employs a current-feedback topology with PNP input transistors; see Figure 58. The matched PNP transistors Q₁ and Q₂ shift the input voltages of both inputs up by a diode drop, and (through the feedback network) shift the output of A₁ and A₂ by approximately 0.8 V. With both inputs and V_REF at single-supply ground (negative power supply), the output of A₁ and A₂ is well within the linear range, allowing differential measurements to be made at the GND level. As a result of this input level-shifting, the voltages at pin 2 and pin 3 are not equal to the respective input terminal voltages (pin 1 and pin 4). For most applications, this inequality is not important because only the gain-setting resistor connects to these pins.

8.3.5 Input Protection

The inputs of the INA826 are individually protected for voltages up to ±40 V. For example, a condition of –40 V on one input and 40 V on the other input does not cause damage. However, if the input voltage exceeds (V–) – 2 V and the signal source current drive capability exceeds 3.5 mA, the output voltage switches to the opposite polarity; see Figure 17. This polarity reversal can easily be avoided by adding resistance of 10 kΩ in series with both inputs.

Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry limits the input current to a safe value of approximately 8 mA. Figure 17 and Figure 18 illustrate this input current limit behavior. The inputs are protected even if the power supplies are disconnected or turned off.

8.3.6 Input Bias Current Return Path

The input impedance of the INA826 is extremely high—approximately 20 GΩ. However, a path must be provided for the input bias current of both inputs. This input bias current is typically 35 nA. High input impedance means that this input bias current changes very little with varying input voltage.

Input circuitry must provide a path for this input bias current for proper operation. Figure 60 shows various provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds the common-mode range of the INA826 and the input amplifiers saturate. If the differential source resistance is low, the bias current return path can be connected to one input (as shown in the thermocouple example in Figure 60). With higher source impedance, using two equal resistors provides a balanced input with possible advantages of lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.

Figure 60. Providing an Input Common-Mode Current Path

8.3.7 Reference Terminal

The output voltage of the INA826 is developed with respect to the voltage on the reference terminal. Often, in dual-supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In single-supply operation, offsetting the output signal to a precise mid-supply level can be useful (for example, 2.5 V in a 5-V supply environment). To accomplish this level shift, a voltage source can be tied to the REF pin to level-shift the output so that the INA826 can drive a single-supply ADC, for example.

For the best performance, keep the source impedance to the REF terminal below 5 Ω. As illustrated in the Functional Block Diagram section, the reference resistor is at one end of a 50-kΩ resistor. Additional impedance at the REF pin adds to this 50-kΩ resistor. The imbalance in the resistor ratios results in degraded common-mode rejection ratio (CMRR).

Figure 61 shows two different methods of driving the reference pin with low impedance. The OPA330 is a low-power, chopper-stabilized amplifier and therefore offers excellent stability over temperature. The OPA330 is available in the space-saving SC70 and even smaller chip-scale package. The REF3225 is a precision reference in the small SOT23-6 package.

Figure 61. Options for Low-Impedance Level Shifting

8.3.8 Dynamic Performance

Figure 23 illustrates that, despite its low quiescent current of only 200 µA, the INA826 achieves much wider bandwidth than other INAs in its class. This achievement is a result of using TI’s proprietary high-speed precision bipolar process technology. The current-feedback topology provides the INA826 with wide bandwidth even at high gains. Settling time also remains excellent at high gain because of a high slew rate of 1 V/µs.

8.3.9 Operating Voltage

The INA826 operates over a power-supply range of 3 V to 36 V (±1.5 V to ±18 V). Supply voltages higher than 40 V (±20 V) can permanently damage the device. Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section of this data sheet.

8.3.10 Error Sources

Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors that result from a change in temperature is normally difficult and costly. Therefore, minimizing these errors is important by choosing high-precision components such as the INA826 that have improved specifications in critical areas that impact the precision of the overall system. Figure 62 shows an example application.

Figure 62. Example Application with G = 10 V/V and 1-V Differential Voltage

Resistor-adjustable INAs such as the INA826 show the lowest gain error in G = 1 because of the inherently well-matched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G = 10 V/V or G = 100 V/V) the gain error becomes a significant error source because of the contribution of the resistor drift of the 24.7-kΩ feedback resistors in conjunction with the external gain resistor. Except for very high gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset drift.

The INA826 offers excellent gain error over temperature for both G > 1 and G = 1 (no external gain resistor). Table 2 summarizes the major error sources in common INA applications and compares the two cases of G = 1 (no external resistor) and G = 10 (5.49-kΩ external resistor). As can be seen in Table 2, although the static errors (absolute accuracy errors) in G = 1 are almost twice as great as compared to G = 10, there are much fewer drift errors because of the much lower gain error drift. In most applications, these static errors can readily be removed during calibration in production. All calculations refer the error to the input for easy comparison and system evaluation.

Table 2. Error Calculation

ERROR SOURCE	ERROR CALCULATION	INA826
		SPECIFICATION	G = 10 ERROR (ppm)	G = 1 ERROR (ppm)
ABSOLUTE ACCURACY AT 25°C
Input offset voltage (μV)	VOSI / VDIFF	150	150	150
Output offset voltage (μV)	VOSO / (G × VDIFF)	700	70	700
Input offset current (nA)	IOS × maximum (RS+, RS–) / VDIFF	5	50	50
CMRR (dB)	VCM / (10CMRR/20 × VDIFF)	104 (G = 10), 84 (G = 1)	63	631
Total absolute accuracy error (ppm)			333	1531
DRIFT TO 105°C
Gain drift (ppm/°C)	GTC × (TA – 25)	35 (G = 10), 1 (G = 1)	2800	80
Input offset voltage drift (μV/°C)	(VOSI_TC / VDIFF) × (TA – 25)	2	160	160
Output offset voltage drift (μV/°C)	[VOSO_TC / ( G × VDIFF)] × (TA – 25)	10	80	800
Offset current drift (pA/°C)	IOS_TC × maximum (RS+, RS–) × (TA – 25) / VDIFF	60	48	48
Total drift error (ppm)			3088	1088
RESOLUTION
Gain nonlinearity (ppm of FS)		5	5	5
Voltage noise (1 kHz)		eNI = 18, eNO = 110	10	10
Total resolution error (ppm)			15	15
TOTAL ERROR
Total error	Total error = sum of all error sources		3436	2634