ZHCSCB3D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
The PCM1860 and PCM1861 hardware-controlled devices offer both master and slave functionality. In master mode, a source master clock (of 256x, 384x, or 512x the sampling rate) can be sourced from either an external crystal (XI/XO) or on an incoming SCK. (see the External Clock-Source Limits section for input rate limitations on SCK sources) The clock from XI and SCK are OR-ed internally, allowing either to be used.
These hardware-controlled devices can generate the other I2S clocks (BCK and LRCK) in master mode (with dividers set in MD0 and MD1) or be a clock slave to MCK,BCK and LRCK. In this scenario, the device auto-detects the clock divider ratio.
In master mode, BCK per LRCK is fixed at 64, and allows up to 32 bits per channel.
Selection of the appropriate master or slave, and clock ratio between MCK and fS can be done using MD0 and MD1.
Table 6 shows the suggested master clock rates for each of the sample rates supported. For slave mode, set BCK per LRCK to 64.
| SAMPLING RATE FREQUENCY
(kHz) |
SYSTEM CLOCK FREQUENCY (MHz) | ||||
|---|---|---|---|---|---|
| 256 × fS | 384 × fS | 512 × fS | |||
| 8.0 | 2.048 | 3.072 | 4.096 | ||
| 16.0 | 4.096 | 6.144 | 8.192 | ||
| 32.0 | 8.1920 | 12.2880 | 16.3840 | ||
| 44.1 | 11.2896 | 16.9344 | 22.5792 | ||
| 48.0 | 12.2880 | 18.4320 | 24.5760 | ||
| 64.0 | 16.3840 | 24.5760 | 32.7680 | ||
| 88.2 | 22.5792 | 33.8688 | 45.1584 | ||
| 96.0 | 24.5760 | 36.8640 | 49.1520 | ||
| 176.4 | 45.1584 | — | — | ||
| 192.0 | 49.1520 | — | — | ||