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ZHCSDD8D October 2014 – December 2019 TPS1H100-Q1

PRODUCTION DATA.

			MAX	UNIT
t_CS,off1	CS settling time from DIAG disabled	V_IN = 5 V, I_load ≥ 5 mA. V_{DIAG_EN} from 5 to 0 V. CS to 10% of sense value.	10	µs
t_CS,on1	CS settling time from DIAG enabled	V_IN = 5 V, I_load ≥ 5 mA. V_{DIAG_EN} from 0 to 5 V. CS to 90% of sense value.	10	µs
t_CS,off2	CS settling time from IN falling edge	V_{DIAG_EN} = 5 V, I_load ≥ 5 mA. IN from 5 to 0 V. CS to 10% of sense value.	10	µs
t_CS,off2	CS settling time from IN falling edge	V_{DIAG_EN} = 5 V, I_load ≥ 5 mA. IN from 5 to 0 V. Current limit triggered.	180	µs
t_CS,on2	CS settling time from IN rising edge	V_VS = 13.5 V, V_{DIAG_EN} = 5 V, I_load ≥ 100 mA. V_IN from 0 to 5 V. CS to 90% of sense value.	150	µs

(1) Value specified by design, not subject to production test.

Figure 2. CS Delay Characteristics

Figure 3. Open-Load Blanking Time Characteristics

Figure 4. Pin Current and Voltage Conventions