In this mode, I²C is enabled and GPIO[3:2] are purposed as 3-state pins (tied to VDD_DIG, GND, or V_IM) and are used to select one of 6 EEPROM pages and one register default setting (2 of 9 states are invalid). GPIO[0] is purposed as a 2-state output synchronization (active-low SYNCN) function, and GPIO[1] is purposed as a 3-state I²C address function to change last 2 bits of I²C address (ADD; 0x0 is GND, 0x1 is V_IM, and 0x3 is VDD_DIG). GPIO[5] is purposed as a multi-state input for the MARGIN function, and GPIO[4] is purposed as an input that enables or disables hardware margining. The GPIO pins are sampled and latched at POR.

GPIO[3:2] allows hardware pin configuration for the PLL synthesizers, the respective input clock selection modes, the crystal input frequency margining option, all output channel blocks comprised of channel muxes, dividers, and output drivers. The GPIO inputs[3:2] are sampled and latched at power-on reset (POR), and select one of 6 EEPROM pages which are custom-programmable. When GPIO[3:2] are left floating, EEPROM is not used and the hardware register default settings are loaded. Table 8-9, Table 8-10, Table 8-11, Table 8-12, and Table 8-13 show the predefined EEPROM configurations according to the GPIO[3:2] pin settings.

The following sections provide a brief overview of each block register settings configured by the GPIO[3:2] pin modes.