The recommended bias supply voltage range for LM5113 is from 4.5 V to 5.5 V. The lower end of this range is governed by the internal undervoltage lockout (UVLO) protection feature of the VDD supply circuit. The upper end of this range is driven by the 7-V absolute maximum voltage rating of the VDD or the GaN transistor gate breakdown voltage limit, whichever is lower. TI recommends keeping a proper margin to allow for transient voltage spikes.

The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage drop do not exceeds the hysteresis specification, VDDH. If the voltage drop is more than hysteresis specification, the device shuts down. Therefore, while operating at or near the 4.5-V range, the voltage ripple on the auxiliary power supply output should be smaller than the hysteresis specification of LM5113 to avoid triggering device shutdown.

A local bypass capacitor should be placed between the VDD and VSS pins. And this capacitor should be located as close to the device as possible. A low-ESR, ceramic surface mount capacitor is recommended. TI recommends using 2 capacitors across VDD and GND: a 100-nF ceramic surface-mount capacitor for high frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220-nF to 10-μF, for IC bias requirements.