ZHCSG17B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The OUTCH10CNTRL1 Register controls Output CH10. Return to Register Map.
BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
[7:2] | RESERVED[5:0] | RW | 0 | RESERVED |
[1] | DIV_DCC_EN_CH10 | RW | 0 | Output CH10 Divider Duty Cycle Correction Enable |
[0] | OUTCH10_DIV_CLKEN | RW | 1 | OUTCH10 Channel Divider Clock Enable. Enables output channel PLL Clock Buffer. |