9.2.1.2 Detail Design Procedure
Designing in the TDP142 requires the following:
- Determine the loss profile on the DisplayPort input (A) and output (B) channels. See Figure 20 for 6 mil trace insertion loss.
- Based upon the loss profile, determine the optimal configuration for the TDP142, to pass electrical compliance. DPEQ[1:0] must be set to appropriate value. For this case, 12-in of FR4 trace approximately equates to 8 dB loss at 4.05 GHz. Therefore, DPEQ1 should be tied 20k ohms to ground and DPEQ0 should be tied 1 kΩ to ground.
- See Figure 18 for information of Source application on using the AC coupling capacitors, control pin resistors, and for recommended decouple capacitors from VCC pins to ground.
- AUX: AUXP should have a 100 kΩ pull-down resistor and AUXN should have a 100 kΩ pull-up resistor. These 100 kΩ resistors must be on the TDP142 side of the 100 nF capacitors.
- HPDIN is used to enable or disable DisplayPort functionality for power saving. The HPD signal should be routed to either pin 23 or pin 32 based on the GPIO/I2C mode.
Table 12. HPD GPIO/I2C Selection
| MODE |
HPD |
| GPIO (I2C_EN = 0) |
Pin 32 |
| I2C (I2C_EN != 0) |
Pin 23 |
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- For the application supporting Dual mode DisplayPort: SNOOPENZ pin must be connected to the CONFIG1 on DisplayPort Receptacle through a buffer like the SN74AHC125. The buffer is needed because the internal pulldown on SNOOPENZ pin is too strong to register a valid VIH when a Dual mode adapter is plugged into the DisplayPort receptacle.
- Configure the TDP142 using the GPIO terminals or the I2C interface:
- GPIO – Using the terminals DPEQ0 and DPEQ1.
- I2C - Refer to the I2C Register Maps and the Programming section for a detail configuration procedures.
- The thermal pad must be connected to ground.