This device has an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input voltage (V_IN) falls below an internal UVLO threshold (V_(UVLO)). This threshold limit ensures that the regulator does not latch into an unknown state during low-input-voltage conditions. If the input voltage has a negative transient that drops below the UVLO threshold and recovers, the regulator shuts down and powers up with a normal power-up sequence when the input voltage is above the required level.