The output dividers can be reset in a deterministic way. This can be achieved using the sync bit or the pin 8 configured for SYNC function using gpio0_input_sel and gpio0_dir_sel. The level of the pin is qualified internally using the reference frequency at the PFD. A low level will mute the outputs. A high level will synchronously release all output dividers to operation, so that all outputs share a common rising edge, see Figure 8-8. The first rising edge can be individually delayed in steps of the respective pre-scaler period, up to 32 cycles using ch1_sync_delay. This allows to compensate external delays like routing mismatch, cables or inherent delays introduced by logic gates in an FPGA design. Each channel can be included or excluded from the SYNC process using ch1_sync_en. ⁽²⁾⁽³⁾

For a deterministic behaviour over power-cycles seen from input to output the reference divider must be set to 1. It should not divide the reference clock nor should the reference doubler be used.

Figure 8-8 Divider Synchronization