米6体育平台手机版

ZHCSGV7F July 2017 – January 2024 CDCI6214

PRODUCTION DATA

8.3.1.5 Zero Delay, Internal and External Path

In zero delay mode the REF input clock is used as reference clock at the PFD. The FB_P clock (LVCMOS) or FB_P/N clock (differential) can be used to feed an external source as feedback clock to the PFD. The external feedback path is recommended for zero delay operation. Moreover there is an additional internal feedback path which is sourced by output channel 2.

Table 8-1 Zero Delay Operation

Operation⁽¹⁾	Reference					Feedback
	REFSEL	ref_mux	ref_mux_src	ip_rdiv	ref_inbuf_ctrl	xin_inbuf_ctrl	zdm_mode	zdm_clocksel	zdm_auto	pll_psfb	GUID-FD0A8D5B-479C-4E33-BCA6-FB389D42D4E8.html#CDCE6214_PLL1_PLL_PSA pll_psa	pll_ndiv	ch2_iod_div ⁽²⁾
Normal PLL, XIN Reference	L	x	0	1	x	0	0	x	x	x	x	x	x
Normal PLL, REF Reference	H	x	0	1	x	x	0	x	x	x	x	x	x
Normal PLL, REF Reference	x	1	1	1	x	x	0	x	x	x	x	x	x
Zero Delay, Internal Feedback	x	1	1	1	A	A	1	0	1	B	B	C	C
Zero Delay, External Feedback	x	1	1	1	A	A	1	1	1	B	B	C	C

(1) 'x' allows any possible bit-field value. An entry of 'A', 'B' or 'C' indicates the same bit-field value.

(2) For internal feedback channel 2 is required. For external feedback the output clock connected to FB_P/N is recommended to have same settings as default PLL feedback path.