A reference clock to the PLL is fed to pins 1 (XOUT/FB_P) and 2 (XIN/FB_N) or to pins 5 (REFP) and 6 (REFN). There are multiple input stages available to adapt to many clock references. The bit-field that controls the reference input type selection is xin_inbuf_ctrl.

The reference mux selects the reference for the PLL and the PLL-bypass path. For debug purposes ip_byp_mux allows to connect the reference divider or doubler output to the clock distribution.

The buffers for the PLL-bypass path can be individually enabled and disabled using ip_byp_en_ch[4:1] and ip_byp_en_y0.

Figure 8-2 Reference Block