ZHCSGV7F
July 2017 – January 2024
CDCI6214
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
EEPROM Characteristics
6.6
Reference Input, Single-Ended and Differential Mode Characteristics (REFP, REFN, FB_P, FB_N)
6.7
Reference Input, Crystal Mode Characteristics (XIN, XOUT)
6.8
General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN)
6.9
Triple Level Input Characteristics (EEPROMSEL, REFSEL)
6.10
Reference Mux Characteristics
6.11
Phase-Locked Loop Characteristics
6.12
Closed-Loop Output Jitter Characteristics
6.13
Output Mux Characteristics
6.14
LVCMOS Output Characteristics
6.15
HCSL Output Characteristics
6.16
LVDS DC-Coupled Output Characteristics
6.17
Programmable Differential AC-Coupled Output Characteristics
6.18
Output Skew and Delay Characteristics
6.19
Output Synchronization Characteristics
6.20
Timing Characteristics
6.21
I2C-Compatible Serial Interface Characteristics (SDA/GPIO2, SCL/GPIO3)
6.22
Timing Requirements, I2C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3)
6.23
Power Supply Characteristics
6.24
Typical Characteristics
7
Parameter Measurement Information
7.1
Parameters
7.1.1
Reference Inputs
7.1.2
Outputs
7.1.3
Serial Interface
7.1.4
Power Supply
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Reference Block
8.3.1.1
Input Stages
8.3.1.1.1
Crystal Oscillator
8.3.1.1.2
LVCMOS
8.3.1.1.3
Differential AC-Coupled
8.3.1.2
Reference Mux
8.3.1.3
Reference Divider
8.3.1.3.1
Doubler
8.3.1.4
Bypass-Mux
8.3.1.5
Zero Delay, Internal and External Path
8.3.2
Phase-Locked Loop
8.3.3
Clock Distribution
8.3.3.1
Output Channel
8.3.3.2
Divider Glitch-Less Update
8.3.4
Control Pins
8.3.4.1
Global and Individual Output Enable: OE and OE_Y[4:1]
8.3.5
Operation Modes
8.3.6
Divider Synchronization - SYNC
8.3.7
EEPROM - Cyclic Redundancy Check
8.3.8
Power Supplies
8.3.8.1
Power Management
8.4
Device Functional Modes
8.4.1
Pin Mode
8.4.2
Serial Interface Mode
8.4.2.1
Fall-Back Mode
8.5
Programming
8.5.1
Recommended Programming Procedure
8.5.2
EEPROM Access
8.5.3
Device Defaults
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Do's and Don'ts
9.4
Initialization Setup
9.5
Power Supply Recommendations
9.5.1
Power-Up Sequence
9.5.2
De-Coupling
9.6
Layout
9.6.1
Layout Guidelines
9.6.2
Layout Examples
10
Register Maps
10.1
CDCI6214 Registers
10.2
EEPROM Map
11
Device and Documentation Support
11.1
Device Support
11.1.1
Development Support
11.1.2
Device Nomenclature
11.2
接收文档更新通知
11.3
支持资源
11.4
Trademarks
11.5
静电放电警告
11.6
术语表
12
Revision History
13
Mechanical, Packaging, and Orderable Information
1
特性
一个可配置的高性能低功耗 PLL,具有 4 路可编程输出
RMS 抖动性能
支持不带 SSC 的第 1/2/3/4 代 PCIe
典型功耗:1.8V 时为 150mW
(2)
通用时钟输入
差分交流耦合或 LVCMOS:1MHz 至 250MHz
晶振:8MHz 至 50MHz
灵活输出频率
44.1kHz 至 350MHz
无毛刺输出分频器切换
四路可独立配置的输出
LVCMOS、
LVDS 或 HCSL 输出
具有可编程摆幅的差分交流耦合输出(与 LVDS、CML-、LVPECL 兼容)
完全集成的 PLL,可配置的环路带宽:
100kHz 至 3MHz
通过单电源或混合电源供电进行电平转换:1.8V、2.5V 和 3.3V
可配置 GPIO
状态信号
最多 4 个独立输出使能端子
输出分频器同步
灵活的配置选项
兼容 I
2
C 的接口:频率高达 400kHz
具有两个页面和外部选择引脚的集成 EEPROM
仅支持 100Ω 系统
工业温度范围:
–40°C
至 85°C
小尺寸:24 引脚 VQFN (4mm × 4mm)
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