The output enable functionality allows to enable or disable all or a specific output buffer. The bypass copy on Y0 is excluded from the global output enable signal. When an output is disabled, it drives a configurable mute-state, ch[4:1]_mute-sel. When the serial interface is deactivated one can use all individual output enable signals at the same time, see mode. The individual output enable signal controls the respective output channel integer divider to gate the clock. Therefore each integer divider needs to be active. When multiple outputs are sourced from the same integer divider, the respective OE signal will enable/disable the output(s). ⁽¹⁾

The individual output enable signal enables and disables the respective output in a deterministic way. Therefore the high and low level of the signal is qualified by counting four cycles of the respective output clock. The following steps can be seen in Figure 8-7:

1. The OE falling edge which disables the outputs.
2. Transition from logic high to logic low / logic low to logic high for Y2 after four rising edges.
3. Transition from logic high to logic low / logic low to logic high for Y1 after four rising edges.
4. The OE rising edge which enables the outputs.
5. Output Y2 starts toggling after four rising edges.
6. Output Y1 starts toggling after four rising edges.

Figure 8-7 Individual Output Enable and Disable