The VCO connects to two individually configurable pre-scaler dividers sourcing the on-chip clock distribution.

The clock distribution consists of four output channels. Each output channel contains a divider with integer division and synchronization capabilities.

A mux after each divider allows to feed the generated frequency to the adjacent output buffers. Thus for single frequency clock generation only a single output divider needs to be active.

The output buffers are compatible to various signaling standards: LVDS, CML-like, LVPECL-like, LVCMOS and HCSL using ch1_outbuf_ctrl.

• HCSL must be directly connected to a load termination to ground. A series resistance can be used to adapt to the trace impedance.
• LVDS requires a differential termination connected between the positive and negative output buffer pins. The termination can be connected directly or using AC-coupling. When using the LVDS output type, set ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, and ch4_1p8vdet to match the VDDO12 and VDDO34.
• CML and LVPECL are only supported in an AC-coupled configuration. The receiver and the termination may only be connected through AC-coupling capacitors to the device pins.
• LVCMOS outputs are designed for capacitive loads only. A series resistance should be used to adapt the driver impedance to the trace impedance. For a typical 50-Ω trace, a resistor between 22 Ω to 33 Ω should be used. The polarity of the positive and negative pins can be adjusted separately.

The output buffers support a wide frequency range of up to 350 MHz. Higher output frequencies up to 700 MHz are functional, but are not covered by electrical specifications.