For this application, TI recommends the following steps:

1. Decide how the device shall receive the register settings to plan for in-system programming of the EEPROM.
2. Choose which operation mode to use on the device (I²C or GPIOs) and which pins are inputs and which are outputs (see registers

   GENERIC0

   ,

   GENERIC1

   , and

   GENERIC2

   ).
3. Consider that the serial interface and the GPIOs are supplied by VDDREF as well as the input pins (for example, a 3.3-V crystal oscillator (XO) driving XIN forces uses 3.3-V I²C).
4. Keep track of which voltage levels the output supplies will have. There are configuration bits in the output channels (see CH1_CTRL5,

   CH2_CTRL5

   , CH3_CTRL5, and CH4_CTRL5).
5. Consider which output frequency has the most stringent phase noise specifications. Select this frequency to decide on the reference and VCO frequency.
6. Cross-check if your specific bandwidth requirement for an external reference can be achieved using the internal loop filter components (see registers PLL1 and PLL2).
7. Optimize the clock distribution using output muxes to run the least amount of blocks to conserve power,
8. For HCSL output buffer format, optimize the signal integrity and slew rate at the receiver input using a series resistor between device pin and the 50 Ω termination to GND.Y1,Y4 provide higher slew rates compared to Y2,Y3.

Use Equation 1 through Equation 4 to calculate the a basic frequency plan or use the provided software TICS Pro to generate settings.

where

• ip_ref_div ≥ 1
• 1 MHz <= f_PFD <= 100 MHz

with

• 2400 <= f_VCO <= 2800
• 0 <= pll_ps <= 2

with

• 0 <= pll_ps[ab] <= 2
• 1 <= ch[4:1]_iod_div <= 16383
• 44.1 kHz <= f_Y[4:1] <= 350 MHz

with

• 1 <= IP_REF_DIV <= 255
• IP_EN_DBLR = 0
• 1 MHz <= f_PFD <= 100 MHz

with

• IP_REF_DIV = 0
• IP_EN_DBLR = 1
• 1 MHz <= f_PFD <= 100 MHz

with

• 2400 <= f_VCO <= 2800
• 0 <= PLL_PS_MODE <= 2

with

• 0 <= PLL_PS[AB]_MODE <= 2
• 1 <= CH[4:1]_IOD_DIV <= 16383
• 44.1 kHz <= f_Y[4:1] <= 350 MHz