米6体育平台手机版

ZHCSGV7F July 2017 – January 2024 CDCI6214

PRODUCTION DATA

8.3.2 Phase-Locked Loop

The CDCI6214 contains a fully integrated phase-locked loop circuit. The error between a reference phase and an internal feedback phase is compared at the phase-frequency-detector. The comparison result is fed to a charge pump that is connected to an integrated loop filter. The control voltage resulting from the loop filter tunes an internal voltage-controlled oscillator (VCO). The frequency of the VCO is fed through a pre-scaler feedback divider (PSFB) and another feedback divider back to the PFD.

The PLL closed-loop bandwidth is configurable using registers PLL0, PLL1, and PLL2.

Integer PLL
PFD operates 1 MHz to 100 MHz
Live Lock-Detector provides PLL lock status on status pin and bit lock_det (there is an additional sticky bit unlock_s)
Integrated selectable loop filter components
For 25-MHz PFD bandwidths between 100 kHz and 3000 kHz can be achieved to optimize PLL to input reference
Voltage-Controlled Oscillator (VCO) tuning range of 2400 to 2800 MHz
VCO is compatible to 0.5% spread spectrum (SSC) references at 100 MHz.

Figure 8-3 Phase-Locked Loop Circuit

Table 8-2 Common Clock Generator Loop Filter Settings

f_VCO in MHz⁽¹⁾	f_PFD in MHz	BW in MHz	Phase Margin in °	Damping Factor	I_CP in mA	C_Pcap IN pF	R_Res IN kΩ	C_Zcap IN pF
f_VCO in MHz⁽¹⁾	f_PFD in MHz	BW in MHz	Phase Margin in °	Damping Factor	pll_cp_up ⁽²⁾	pll_lf_pcap	pll_lf_res	pll_lf_zcap
2400	25	0.51	67	0.9	2.0	17.5	2.5	450
2400	50	0.97	67	1.3	2.0	17.5	2.5	450
2400	100	1.41	68	1.2	2.4	17.5	1.5	450
2457.6	61.44	1.04	67	1.4	1.8	17.5	2.5	450
2500	25	0.49	67	0.9	2.0	17.5	2.5	450
2500	50	0.93	68	1.3	2.0	17.5	2.5	450
2680	67	0.38	67	1.3	0.2	19.5	5.5	480
2688	48	0.93	68	1.3	1.5	17.5	2.5	480
2688	96	0.36	67	1.0	0.2	19.5	3.5	480
2800	50	1.00	68	1.0	2.6	17.5	1.5	450
2800	100	1.00	68	1.0	1.3	17.5	1.5	450

(1) All values typical design targets.

(2) Program same value to pll_cp_dn.