8.2.3 Parallel Operation

The TPS50601A-SP can be configured in master-slave mode to provide 12-A output current as shown in Figure 24.

Figure 24. Parallel Configuration Showing Master and Slave

The design procedure to configure the master-slave operation using the internal oscillator is as follows:

• The RT pin of the master device must be left floating. This achieves 2 purposes, to set the frequency to 500 kHz (typical) using the internal oscillator and to configure the SYNC pin of the master device as an output pin with a 500-kHz clock, 180° in phase respect to the internal oscillator of the master device. For more details, see Adjustable Switching Frequency and Synchronization (SYNC) section.
• The RT pin on slave device should be connected to a resistor such that the frequency of the slave device is within 5% of the master's frequency, 500 kHz in this case. See Figure 18 for reference.
• SYNC pin of the master device must be connected to the SYNC pin of the slave device.
• Only a single feedback network is needed connected to the VSENSE pin of the master device. Therefore, both VSENSE pins must be connected.
• Only a single compensation network is needed connected to the COMP pin of the master device. Therefore both COMP pins must be connected.
• Only a single soft start capacitor is needed connected to the SS pin of the master device. Therefore both SS pins must be connected.
• Only a single enable signal (or resistor divider) is needed connected to the EN pin of the master device. Therefore, both EN pins must be connected.
• Since the master device controls the compensation, soft start and enable networks, the factor of 2 must be taken into account when calculating the components associated with these pins.

The master-slave mode can also be implemented using an external clock. In such case, a different frequency other than 500 kHz can be used. When using an external clock, only the RT and SYNC pins configuration varies as follows:

• RT pins of both master and slave device must be connected to a resistor matching the frequency of the external clock being used. See Figure 18 for reference.
• The external clock is connected to the SYNC pin of the master device. A 10-kΩ resistor to GND should be connected to the SYNC pin as well.
• An inverted clock (180° in phase respect to the master device) must be connected to the SYNC pin of the slave device. A 10-kΩ resistor to GND should be connected to the SYNC pin as well.