ZHCSI15L June   2006  – May 2018 TPS65023 , TPS65023B

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 6.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 6.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 6.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 6.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 6.11 I2C Timing Requirements for TPS65023B
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 7.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 7.3.3  Power Save Mode Operation
      4. 7.3.4  Low Ripple Mode
      5. 7.3.5  Soft-Start
      6. 7.3.6  100% Duty Cycle Low Dropout Operation
      7. 7.3.7  Active Discharge When Disabled
      8. 7.3.8  Power-Good Monitoring
      9. 7.3.9  Low-Dropout Voltage Regulators
      10. 7.3.10 Undervoltage Lockout
      11. 7.3.11 Power-Up Sequencing
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 System Reset + Control Signals
        1. 7.5.1.1 DEFLDO1 and DEFLDO2
        2. 7.5.1.2 Interrupt Management and the INT Pin
      2. 7.5.2 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 VERSION Register Address: 00h (Read Only)
      2. 7.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 7.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 7.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 7.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
      6. 7.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 7.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 7.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 7.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Voltage Connection
      2. 8.1.2 Unused Regulators
      3. 8.1.3 Reset Condition of DCDC1
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection for the DC-DC Converters
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Voltage Selection
        5. 8.2.2.5 VRTC Output
        6. 8.2.2.6 LDO1 and LDO2
        7. 8.2.2.7 TRESPWRON
        8. 8.2.2.8 VCC Filter
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Requirements for Supply Voltages Below 3.0 V
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 11.1.2 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 相关链接
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息

4 修订历史记录

Changes from K Revision (December 2015) to L Revision

  • Changed 更改了数据表的标题Go
  • Replaced references of TI PowerPAD IC package with thermal pad Go
  • Added 增加了器件支持 和文档支持 部分Go
  • Changed 静电放电注意事项 声明Go

Changes from J Revision (September 2011) to K Revision

  • Added 添加了 ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go

Changes from I Revision (July 2010) to J Revision

  • Added Thermal Information Table and deleted Dissipation Ratings TableGo

Changes from H Revision (December 2009) to I Revision

  • Added I2C 的 串行 接口Go
  • Added TPS65023B 器件规格Go
  • 添加了 TPS65023B 器件的订购信息。Go
  • Added specs for TPS65023B deviceGo
  • Changed "VBACKUP threshold" test condition typographical error from "VBACKUP falling" to "VBACKUP rising"Go
  • Added specs for TPS65023B deviceGo
  • Added Differences table for TPS65023 and TPS65023B devicesGo

Changes from G Revision (October 2008) to H Revision

  • Changed IO(DCDC1) MAX from: 1500 mA to: 1700 mAGo
  • Added High level input voltage for the SDAT pinGo
  • Changed IO from:1500 mA MIN to 1700 mA Go
  • Changed IO maximum from:1.5 A to: 1.7 A for VDCDC1 fixed and adjustable output voltage test condition specs.Go
  • Changed IO maximum from: 1500 mA to: 1700 mA for VDCDC1 Load Regulation test conditionGo
  • Changed VDCDC1 "soft-start ramp time" spec to: "tStart and tRamp" specifications with MIN TYP MAX values.Go
  • Changed VDCDC2 "soft-start ramp time" spec To: "tStart and tRamp" specifications with MIN TYP MAX values.Go
  • Changed VDCDC3 "soft-start ramp time" spec To: "tStart and tRamp" specifications with MIN TYP MAX values.Go
  • Changed FBD graphic to show 1700 mA for DCDC1 Buck ConverterGo
  • Changed text string from: "1.2 V or 1.8 V" to: "1.2 V to 1.6 V" in the STEP-DOWN CONVERTERS.,VDCDC1.... description.Go
  • Changed graphic entity to the one used in the Application Note SLVA273Go

Changes from F Revision (July 2007) to G Revision

  • Changed the Interrupt Management and the INT Pin section.Go

Changes from E Revision (January 2007) to F Revision

  • Changed text string from: "If it is tied to VCC, the default is 2.5 V" To: "If it is tied to VCC, the default is 3.3 V"Go

Changes from D Revision (December 2006) to E Revision

  • Changed LDO1 output voltage range from: 3.3 to: 3.3Go
  • Changed text string from: "VDCDC2 converter defaults to 1.8 V or 2.5 V" to: "VDCDC2 converter defaults to 1.8 V or 3.3 V"Go

Changes from C Revision (October 2006) to D Revision

  • Changed Typical Configuration for Ti DaVinci ProcessorsGo

Changes from B Revision (June 2006) to C Revision

Changes from A Revision (June 2006) to B Revision

  • Changed 从 97% 效率的 1.5A 降压转换器更改为 90% 效率的 1.7A 降压转换器Go
  • Changed 从 6mm × 6mm QFN 封装更改为 5mm × 5mm QFN 封装Go
  • Changed 从 RHA 封装更改为 RSB 封装Go
  • Changed from:O(DCDC2) to: IO(DCDC1)Go
  • Changed Forward current limit - removed TBD and added valuesGo
  • Changed Fixed output voltage - removed TBD and added valuesGo
  • Changed Fixed output voltage - removed TBD and added valuesGo
  • Added VINDCDC3 = 3.6 V to Maximum output currentGo
  • Changed Fixed output voltage - removed TBD and added valuesGo
  • Changed Figure 3 (DVS Timing)Go
  • Changed Figure 11 (Graph - DCDC2: OUTPUT VOLTAGE)Go
  • Added Figure 12 (Graph - DCDC3: OUTPUT VOLTAGE )Go
  • Changed Figure 20 (Graph - VDCDC2 OUTPUT VOLTAGE RIPPLE)Go
  • Added Reset Condition of DCDC1 InformationGo
  • Changed Typical Configuration for Ti DaVinci ProcessorsGo
  • Changed from: TPS65023 typically use a 3.3 μH output inductor to: TPS65023 typically use a 2.2 μH output inductorGo
  • Changed from: VDCDC3 to: VDCDC1Go
  • Changed from: VDEFDCDC3 to: DEFDCDC1Go
  • Changed from: 2.5 V to 3.3 V (Table 20)Go

Changes from * Revision (May 2006) to A Revision

  • Changed Electrical Characteristics: VDCDC1 Step-Down ConverterGo
  • Changed Electrical Characteristics: VDCDC3 Step-Down Converter Go
  • Changed CON_CTRL Register Address - Column B0 default value changed from 1 to 0.Go
  • Changed VDCDC# to VDCDC1Go
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