The printed circuit board (PCB) requires careful layout to minimize current loop areas and track lengths, especially when using single-sided PCBs.

• Place a ceramic MLCC bypass capacitor as close as possible to REG and GND.
• Avoid connecting VD1 or VD2 and VSS sense points at locations where stray inductance is added to the SR MOSFET package inductance, as this tends to turn off the SR prematurely.
• Run a trace from the VD1 or VD2 pin directly to the MOSFET drain pad to avoid sensing voltage across the stray inductance in the SR drain current path.
• Run a trace from the VSS pin directly to the MOSFET source pad to avoid sensing voltage across the stray inductance in the SR source current path. Because this trace shares both the gate driver path and the MOSFET voltage sensing path, TI recommends making this trace as short as possible.
• Run parallel traces from VG1 or VG2 and PGND to the SR MOSFET. Include a series gate resistance to dampen ringing if it is needed.