UCC24624 uses the REG pin voltage to detect UVLO instead of the VDD pin voltage. When the REG voltage has not yet reached the VREG_ON threshold, or has fallen below the UVLO threshold VREG_OFF, the device operates in the low-power UVLO mode. In this mode, most internal functions are disabled and VDD current is IVDD_START. If the REG pin is above 2 V, there is an active pull down from VG1 and VG2 to PGND to prevent the SR from falsely turning on due to noise. When the REG pin voltage is less than 2 V, there is a weak pull down from VG1 and VG2 to PGND and this also prevents noise from turning on SR MOSFETs. The device exits UVLO mode when REG increases above the VREG_ON threshold.