The PG circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The PG circuit asserts whenever FB, V_IN, or EN are below their thresholds. The PG operation versus the output voltage is shown in Figure 8-5, which is described by Table 8-8.

Figure 8-5 Typical PG Operation

The PG pin is open-drain, and connecting a pullup resistor to an external supply enables others devices to receive Power Good as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices.

To ensure proper operation of the PG circuit, the pullup resistor value must be from 10 kΩ and 100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the PG transistor, and the upper limit of 100 kΩ results from the maximum leakage current at the PG node. If the pullup resistor is outside of this range, then the PG signal may not read a valid digital logic level.

Using a large C_FF with a small C_NR/SS causes the PG signal to incorrectly indicate that the output voltage has settled during turnon. The C_FF time constant must be greater than the soft-start time constant to ensure proper operation of the PG during start-up. For a detailed description, see Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator.

The state of PG is only valid when the device operates above the minimum supply voltage. During short brownout events and at light loads, PG does not assert because the output voltage (therefore V_FB) is sustained by the output capacitance.