ZHCSL68C April   2017  – December 2020 TPS7A84A

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: General
    6. 6.6 Electrical Characteristics: TPS7A8400A
    7. 6.7 Electrical Characteristics: TPS7A8401A
    8. 6.8 Typical Characteristics: TPS7A8400A
    9. 6.9 Typical Characteristics: TPS7A8401A
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft Start (NR/SS)
        2. 7.3.2.2 Internal Sequencing
          1. 7.3.2.2.1 Enable (EN)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLO) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PG)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICL)
        2. 7.3.3.2 Thermal Protection (Tsd)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection
        1. 8.1.1.1 Adjustable Operation
        2. 8.1.1.2 ANY-OUT Programmable Output Voltage
        3. 8.1.1.3 ANY-OUT Operation
        4. 8.1.1.4 Increasing ANY-OUT Resolution for LILO Conditions
        5. 8.1.1.5 Current Sharing
        6. 8.1.1.6 Recommended Capacitor Types
        7. 8.1.1.7 Input and Output Capacitor Requirements (CIN and COUT)
        8. 8.1.1.8 Feed-Forward Capacitor (CFF)
        9. 8.1.1.9 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Circuit Soft-Start Control (NR/SS)
          1. 8.1.2.1.1 Inrush Current
        2. 8.1.2.2 Undervoltage Lockout (UVLO)
        3. 8.1.2.3 Power-Good (PG) Function
      3. 8.1.3 AC and Transient Performance
        1. 8.1.3.1 Power-Supply Rejection Ratio (PSRR)
        2. 8.1.3.2 Output Voltage Noise
        3. 8.1.3.3 Optimizing Noise and PSRR
          1. 8.1.3.3.1 Charge Pump Noise
        4. 8.1.3.4 Load Transient Response
      4. 8.1.4 DC Performance
        1. 8.1.4.1 Output Voltage Accuracy (VOUT)
        2. 8.1.4.2 Dropout Voltage (VDO)
          1. 8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation
      5. 8.1.5 Sequencing Requirements
      6. 8.1.6 Negatively Biased Output
      7. 8.1.7 Reverse Current Protection
      8. 8.1.8 Power Dissipation (PD)
        1. 8.1.8.1 Estimating Junction Temperature
        2. 8.1.8.2 Recommended Area for Continuous Operation (RACO)
    2. 8.2 Typical Applications
      1. 8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Models
        2. 11.1.1.2 Spice Models
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表

6.7 Electrical Characteristics: TPS7A8401A

Over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.4 V (whichever is greater), VBIAS = open, VOUT(nom) = 0.5 V(1), OUT connected to 50 Ω to GND(2), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF, CNR/SS =0nF, without CFF, and PG pin pulled up to VIN with 100 kΩ, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB Feedback voltage 0.5 V
VNR/SS NR/SS pin voltage 0.5 V
VOUT Output voltage Range Using the ANY-OUT pins 0.5 – 1.2% 2.075 + 1.0% V
Range Using external resistors(3) 0.5 – 1.2% 5.15 + 1.0%
Accuracy(3) (4) 0.5 V ≤ VOUT ≤ 5.15(5) V, 5 mA ≤ IOUT ≤ 3 A, over VIN –1.25% 1.25%
Accuracy with BIAS VIN = 1.1 V, VOUT = 0.5V, 5 mA ≤ IOUT ≤ 3 A,
3.0 V ≤ VBIAS ≤ 6.5 V		 –1.0% 1.1%
ΔVOUT/
ΔVIN 		Line regulation IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V 0.03 mV/V
ΔVOUT/
ΔIOUT 		Load regulation 5 mA ≤ IOUT ≤ 3 A, 3.0 V ≤ VBIAS ≤ 6.5 V,
VIN = 1.1 V		 0.07 mV/A
5 mA ≤ IOUT ≤ 3 A 0.08
5 mA ≤ IOUT ≤ 3 A, VOUT = 5.15 V 0.04
VDO Dropout voltage VIN = 1.4 V, IOUT = 3 A, VFB = 0.5 V – 3% 155 260 mV
VIN = 5.4 V, IOUT = 3 A, VFB = 0.5 V – 3% 225 375
VIN = 5.6 V, IOUT = 3 A, VFB = 0.5 V – 3% 270 490
VIN = 1.1 V, VBIAS = 5 V,
IOUT = 3 A, VFB = 0.5 V – 3%		 110 180
ILIM Output current limit VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V		 3.3 4.2 4.75 A
ISC Short-circuit current limit RLOAD = 20 mΩ, under foldback operation 2.5 A
PSRR Power-supply ripple rejection VIN – VOUT = 0.4 V,
IOUT = 3 A, CNR/SS = 100 nF, CFF = 10 nF,
COUT = 22 μF		 f = 10 kHz,
VOUT = 0.5 V,
VBIAS = 5.0 V		 42 dB
f = 500 kHz, VOUT = 0.5 V, VBIAS = 5.0 V 39
f = 10 kHz,
VOUT = 5.0 V		 40
f = 500 kHz, VOUT = 5.0 V 25
Vn Output noise voltage BW = 10 Hz to 100 kHz, VIN = 1.1 V,
VOUT = 0.5 V, VBIAS = 5.0 V, IOUT = 3 A,
CNR/SS = 100 nF, CFF = 10 nF,
COUT = 47 μF || 10μF || 10μF		 4.8 μVRMS
BW = 10 Hz to 100 kHz,
VOUT = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF,
CFF = 10 nF, COUT = 47 μF || 10μF || 10μF		 15.8
IGND GND pin current VIN = 6.5 V, IOUT = 5 mA 3 4.3 mA
VIN = 1.4 V, IOUT = 3 A 4.3 5.5
Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V 1.2 25 μA
VIT(PG) PG pin threshold For falling VOUT 80% x VOUT 86% x VOUT 91% x VOUT V
VHYS(PG) PG pin hysteresis For rising VOUT 5% x VOUT V
(1) VOUT(nom) is the calculated VOUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, VOUT(nom) is the expected VOUT value set by the external feedback resistors.
(2) This 50-Ω load is disconnected when the test conditions specify an IOUT value.
(3) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
(4) The device is not tested under conditions where VIN > VOUT + 1.7 V and IOUT = 3 A, because the power dissipation is higher than the maximum rating of the package.
(5) For VOUT ≤ 5 V, VIN = VOUT + 0.4 V; For VOUT > 5 V, VIN = VOUT + 0.45 V
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