米6体育平台手机版_好二三四详情

Sample rate (max) (Msps) 160 Resolution (bps) 16 Number of input channels 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 1400 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2, 2.4 Power consumption (typ) (mW) 1340 Architecture Pipeline SNR (dB) 78 ENOB (bit) 12.3 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 160 Resolution (bps) 16 Number of input channels 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 1400 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2, 2.4 Power consumption (typ) (mW) 1340 Architecture Pipeline SNR (dB) 78 ENOB (bit) 12.3 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer No
VQFNP (NKE) 68 100 mm² 10 x 10
  • Low Power Consumption
  • On-Chip Precision Reference and Sample-and-Hold Circuit
  • On-Chip Automatic Calibration During Power-Up
  • Dual Data Rate LVDS Output Port
  • Dual Supplies: 1.8V and 3.0V Operation
  • Selectable Input Range: 2.4 and 2.0 VPP
  • Sampling Edge Flipping with Clock Divider by 2 Option
  • Internal Clock Divide by 1 or 2
  • On-Chip Low Jitter Duty-Cycle Stabilizer
  • Power-Down and Sleep Modes
  • Output Fixed Pattern Generation
  • Output Clock Position Adjustment
  • 3-Wire SPI
  • Offset Binary or 2's Complement Data Format
  • 68-Pin VQFN Package (10x10x0.8, 0.5mm Pin-Pitch)

Key Specifications

  • Resolution: 16 Bits
  • Conversion Rate: 160 MSPS
  • SNR (@FIN = 30 MHz): 78 dBFS (typ)
  • SNR (@FIN = 197 MHz): 76 dBFS (typ)
  • SFDR (@FIN = 30 MHz): 95 dBFS (typ)
  • SFDR (@FIN = 197 MHz): 89 dBFS (typ)
  • Full Power Bandwidth: 1.4 GHz (typ)
  • Power Consumption:
    • Core per channel: 612 mW (typ)
    • LVDS Driver: 117 mW (typ)
    • Total: 1.3W (typ)
  • Operating Temperature Range (-40°C ~ 85°C)
  • Low Power Consumption
  • On-Chip Precision Reference and Sample-and-Hold Circuit
  • On-Chip Automatic Calibration During Power-Up
  • Dual Data Rate LVDS Output Port
  • Dual Supplies: 1.8V and 3.0V Operation
  • Selectable Input Range: 2.4 and 2.0 VPP
  • Sampling Edge Flipping with Clock Divider by 2 Option
  • Internal Clock Divide by 1 or 2
  • On-Chip Low Jitter Duty-Cycle Stabilizer
  • Power-Down and Sleep Modes
  • Output Fixed Pattern Generation
  • Output Clock Position Adjustment
  • 3-Wire SPI
  • Offset Binary or 2's Complement Data Format
  • 68-Pin VQFN Package (10x10x0.8, 0.5mm Pin-Pitch)

Key Specifications

  • Resolution: 16 Bits
  • Conversion Rate: 160 MSPS
  • SNR (@FIN = 30 MHz): 78 dBFS (typ)
  • SNR (@FIN = 197 MHz): 76 dBFS (typ)
  • SFDR (@FIN = 30 MHz): 95 dBFS (typ)
  • SFDR (@FIN = 197 MHz): 89 dBFS (typ)
  • Full Power Bandwidth: 1.4 GHz (typ)
  • Power Consumption:
    • Core per channel: 612 mW (typ)
    • LVDS Driver: 117 mW (typ)
    • Total: 1.3W (typ)
  • Operating Temperature Range (-40°C ~ 85°C)

The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 160 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16DV160 can be re-calibrated at any time through the 3-wire Serial Peripheral Interface (SPI). An integrated low noise and stable voltage reference and differential reference buffer amplifier eases board level design. The on-chip duty cycle stabilizer with low additive jitter allows a wide range of input clock duty cycles without compromising dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver block can be easily verified and optimized via fixed pattern generation and output clock position features. The digital data is provided via dual data rate LVDS outputs – making possible the 68-pin, 10 mm x 10 mm VQFN package. The ADC16DV160 operates on dual power supplies of +1.8V and +3.0V with a power-down feature to reduce power consumption to very low levels while allowing fast recovery to full operation.

The ADC16DV160 is a monolithic dual channel high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 160 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16DV160 can be re-calibrated at any time through the 3-wire Serial Peripheral Interface (SPI). An integrated low noise and stable voltage reference and differential reference buffer amplifier eases board level design. The on-chip duty cycle stabilizer with low additive jitter allows a wide range of input clock duty cycles without compromising dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and a receiver block can be easily verified and optimized via fixed pattern generation and output clock position features. The digital data is provided via dual data rate LVDS outputs – making possible the 68-pin, 10 mm x 10 mm VQFN package. The ADC16DV160 operates on dual power supplies of +1.8V and +3.0V with a power-down feature to reduce power consumption to very low levels while allowing fast recovery to full operation.

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类型 标题 下载最新的英语版本 日期
* 数据表 Dual Channel, 16-Bit, 160 MSPS Analog-to-Digital Converter with DDR LVDS Outputs 数据表 (Rev. H) 2013年 2月 19日
应用手册 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015年 5月 22日
应用手册 Signal Chain Noise Figure Analysis 2014年 10月 29日
应用手册 Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013年 7月 19日
EVM 用户指南 AN-1942 LMH6517 Evaluation Board (Rev. B) 2013年 4月 26日
应用手册 AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 2013年 4月 26日
应用手册 Between the Amplifier and ADC: Managing Filter Loss in Communications Systems (Rev. B) 2013年 4月 26日
应用手册 Drivng HSpeed ADCs w/LMH6521 DVGA for High IF AC-Coupled Apps (Rev. A) 2013年 4月 26日
用户指南 High-IF Sub-sampling Receiver Subsystem User Guide 2012年 1月 27日
EVM 用户指南 ADC16DV160HFEB Evaluation Board User Guide 2012年 1月 25日

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ADC16DV160HFEB — ADC16DV160HFEB 评估板

This Design Kit is designed to ease evaluation and design-in of National Semiconductor's ADC16DV160 Dual Channel 16-bit Analog-to-Digital Converter with DDR LVDS outputs, which operates at speeds up 160 Msps.

The evaluation board can be used by connecting the board to the WaveVision 5.1 Data Capture (...)

用户指南: PDF
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WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

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支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
高速 ADC (≥10MSPS)
ADC08D1020 8 位、双路 1.0GSPS 或单路 2.0GSPS 模数转换器 (ADC) ADC08D1520 8 位、双路 1.5GSPS 或单路 3.0GSPS 模数转换器 (ADC) ADC10D1000 10 位、双通道 1.0GSPS 或单路 2.0GSPS 模数转换器 (ADC) ADC10D1500 10 位、双通道 1.5GSPS 或单通道 3.0GSPS 模数转换器 (ADC) ADC10DV200 双通道、10 位、200MSPS 模数转换器 (ADC) ADC12D1000 12 位、双通道 1.0GSPS 或单通道 2.0GSPS 模数转换器 (ADC) ADC12D1000RF 12 位、双通道 1.0GSPS 或单通道 2.0GSPS 射频采样模数转换器 (ADC) ADC12D1600 12 位、双通道 1.6GSPS 或单通道 3.2GSPS 模数转换器 (ADC) ADC12D1600RF 12 位双通道 1.6GSPS 或单通道 3.2GSPS 射频采样模数转换器 (ADC) ADC12D1800 12 位、双通道 1.8GSPS 或单通道 3.6GSPS 模数转换器 (ADC) ADC12D1800RF 12 位、双通道 1.8GSPS 或单通道 3.6GSPS、射频采样模数转换器 (ADC) ADC12D500RF 12 位、双通道 500MSPS 或单通道 1.0GSPS 射频采样模数转换器 (ADC) ADC12D800RF 12 位、双通道 800MSPS 或单通道 1.6GSPS 射频采样模数转换器 (ADC) ADC14DC080 双通道、14 位、80MSPS、1.0GHz 输入带宽模数转换器 (ADC) ADC16DV160 双通道、16 位、160MSPS 模数转换器 (ADC) ADC16V130 16 位、130MSPS 模数转换器 (ADC)
硬件开发
评估板
ADC08D1520RB ADC08D1520RB:低功耗、8 位、双路 1.5 GSPS 或单路 3.0 GSPS 模数转换器参考板 ADC12D1600RB 12 位双路 1.6/1.8 GSPS 或单路 3.2/3.6 GSPS A/D 转换器参考板 ADC16DV160HFEB ADC16DV160HFEB 评估板 LM98640CVAL 具有 LVDS 输出的双通道、14 位、40 MSPS 模拟前端 WAVEVSN-BRD-5.1 WaveVision 5 数据捕获板(5.1 版)
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应用软件和框架
WAVEVISION5 Data Acquisition and Analysis Software
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PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源米6体育平台手机版_好二三四系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短米6体育平台手机版_好二三四上市时间并降低开发成本。

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封装 引脚 CAD 符号、封装和 3D 模型
VQFNP (NKE) 68 Ultra Librarian

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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