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米6体育平台手机版_好二三四详情

Arm CPU 1 Arm9 Arm (max) (MHz) 375, 456 Coprocessors PRU-ICSS CPU 32-bit Display type 1 LCD Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Power supply solution TPS650061 Operating temperature range (°C) -40 to 105
Arm CPU 1 Arm9 Arm (max) (MHz) 375, 456 Coprocessors PRU-ICSS CPU 32-bit Display type 1 LCD Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Power supply solution TPS650061 Operating temperature range (°C) -40 to 105
NFBGA (ZCE) 361 169 mm² 13 x 13 NFBGA (ZWT) 361 256 mm² 16 x 16
  • 375- and 456-MHz ARM926EJ-S RISC MPU
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address Space
      • 16-Bit mDDR SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
      • Register 30 of Each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Transmit and Receive Clocks
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Transmit and Receive Clocks
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and Data Converters
    • Data Width on Both Channels is 8- to 16-Bit Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
  • 361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm Ball Pitch
  • Commercial or Extended Temperature
  • 375- and 456-MHz ARM926EJ-S RISC MPU
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address Space
      • 16-Bit mDDR SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
      • Register 30 of Each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Transmit and Receive Clocks
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Transmit and Receive Clocks
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • Video Port Interface (VPIF):
    • Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video Capture Channels
    • Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
  • Universal Parallel Port (uPP):
    • High-Speed Parallel Interface to FPGAs and Data Converters
    • Data Width on Both Channels is 8- to 16-Bit Inclusive
    • Single-Data Rate or Dual-Data Rate Transfers
    • Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
  • 361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm Ball Pitch
  • Commercial or Extended Temperature

The AM1806 ARM Microprocessor is a low-power applications processor based on ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: one USB2.0 OTG interface; two inter-integrated circuit (I2C Bus) interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two external memory interfaces; an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The universal parallel port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) is included providing a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows debugger interface for visibility into source code execution.

The AM1806 ARM Microprocessor is a low-power applications processor based on ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: one USB2.0 OTG interface; two inter-integrated circuit (I2C Bus) interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two external memory interfaces; an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The universal parallel port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) is included providing a flexible video I/O port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows debugger interface for visibility into source code execution.
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类型 标题 下载最新的英语版本 日期
* 数据表 AM1806 ARM Microprocessor 数据表 (Rev. F) PDF | HTML 2014年 3月 21日
* 勘误表 AM1806 ARM Microprocessor Silicon Errata (Revs 2.3, 2.1 and 2.0) (Rev. H) 2014年 9月 17日
用户指南 ARM 优化 C/C++ 编译器 v20.2.0.LTS (Rev. W) PDF | HTML 英语版 (Rev.W) PDF | HTML 2023年 4月 13日
用户指南 ARM 汇编语言工具 v20.2.0.LTS (Rev. Z) PDF | HTML 英语版 (Rev.Z) PDF | HTML 2023年 4月 13日
应用手册 高速接口布局指南 (Rev. J) PDF | HTML 英语版 (Rev.J) PDF | HTML 2023年 3月 23日
用户指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020年 6月 1日
应用手册 Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x 2019年 12月 20日
用户指南 ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 2019年 6月 3日
用户指南 ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 2019年 6月 3日
应用手册 Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx 2019年 4月 25日
应用手册 General Hardware Design/BGA PCB Design/BGA 2019年 2月 22日
应用手册 OMAP-L13x / C674x / AM1x schematic review guidelines PDF | HTML 2019年 2月 14日
应用手册 Using the AM18xx Bootloader (Rev. D) PDF | HTML 2019年 1月 22日
用户指南 ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 2018年 11月 19日
用户指南 ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 2018年 11月 19日
用户指南 How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018年 9月 24日
用户指南 PRU Assembly Instruction User Guide 2018年 2月 16日
用户指南 ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 2018年 1月 16日
用户指南 ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 2018年 1月 16日
用户指南 ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 2017年 9月 30日
用户指南 ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 2017年 9月 30日
用户指南 ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 2017年 6月 21日
用户指南 ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 2017年 6月 21日
用户指南 AM1806 ARM Microprocessor Technical Reference Manual (Rev. C) 2016年 9月 12日
用户指南 ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 2016年 4月 30日
用户指南 ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 2016年 4月 30日
技术文章 Spring has sprung. A sale has sprung. PDF | HTML 2016年 4月 4日
用户指南 ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 2014年 11月 5日
用户指南 ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 2014年 11月 5日
应用手册 AM18xx Pin Multiplexing Utility (Rev. A) 2011年 12月 6日
应用手册 Powering the AM1806, AM1808, and AM1810 with the TPS650061 2011年 9月 6日
应用手册 High-Vin, High-Efficiency Power Solution Using DC/DC Converter With DVFS (Rev. C) 2011年 8月 29日
应用手册 Medium Integrated Power Solution Using a Dual DC/DC Converter and an LDO (Rev. B) 2011年 8月 29日
应用手册 Powering OMAP-L132/L138, C6742/4/6, and AM18x with TPS65070 (Rev. B) 2011年 8月 29日
应用手册 Simple Power Solution Using LDOs (Rev. B) 2011年 8月 29日
应用手册 AM18x power consumption summary 2010年 8月 30日
应用手册 High-Efficiency Power Solution Using DC/DC Converters With DVFS (Rev. A) 2010年 5月 5日
应用手册 High-Integration, High-Efficiency Power Solution Using DC/DC Converters w/DVFS (Rev. A) 2010年 5月 5日
应用手册 TMS320C6748/46/42 & OMAP-L132/L138 USB Downstream Host Compliance Testing 2009年 8月 17日
应用手册 TMS320C6748/46/42 & OMAP-L1x8 USB Upstream Device Compliance Testing 2009年 8月 17日
应用手册 TMS320C674x/OMAP-L1x USB Compliance Checklist 2009年 3月 12日
应用手册 Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008年 7月 17日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针（仿真器）。与低成本的 XDS110 和高性能的 XDS560v2 相比，XDS200 在低成本和高性能之间实现了平衡；并在单个仓体中支持广泛的标准（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪，则需要使用 XDS560v2 PRO TRACE。

XDS200 通过 TI 20 引脚连接器（带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)

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调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的米6体育平台手机版_好二三四，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意，它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪，需要 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (480Mbps) (...)

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TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

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XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

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软件开发套件 (SDK)

LINUXEZSDK-AM18X — 用于 AM1808、AM1806 和 AM1802 的 Linux EZ SDK

SITARA LINUX SDK

Linux Software Development Kits (SDK) provide Sitara™ developers with an easy set up and quick out-of-box experience that is specific to and highlights the features of TI's ARM processors. Launching demos, benchmarks and applications is a snap with the included graphical user (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
基于 Arm 的处理器
AM1806 — Sitara 处理器: Arm9，LPDDR，DDR2，显示 AM1810 — Sitara 处理器: Arm9，LPDDR，DDR2，显示，以太网，PROFIBUS
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软件开发套件 (SDK)

LINUXSDK-AM17X — 用于 AM1707 和 AM1705 的 Linux SDK

SITARA LINUX SDK

Linux Software Development Kits (SDK) provide Sitara™ developers with an easy set up and quick out-of-box experience that is specific to and highlights the features of TI's ARM processors. Launching demos, benchmarks and applications is a snap with the included graphical user (...)

支持的米6体育平台手机版_好二三四和硬件

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基于 Arm 的处理器
AM1806 — Sitara 处理器: Arm9，LPDDR，DDR2，显示 AM1810 — Sitara 处理器: Arm9，LPDDR，DDR2，显示，以太网，PROFIBUS AM3892 — Sitara 处理器: Arm Cortex-A8、HDMI AM3894 — Sitara 处理器: Arm Cortex-A8、3D 图形、HDMI
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软件开发套件 (SDK)

PRU-SWPKG — 可编程实时单元 (PRU) 软件支持包

The PRU Software Support Package is an add-on package that provides a framework and examples for developing software for the Programmable Real-time Unit sub-system and Industrial Communication Sub-System (PRU-ICSS) in the supported TI processors.  The PRU-ICSS achieves deterministic, real-time (...)

支持的米6体育平台手机版_好二三四和硬件

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基于 Arm 的处理器
AM1802 — Sitara 处理器: Arm9，LPDDR，DDR2，以太网 AM1806 — Sitara 处理器: Arm9，LPDDR，DDR2，显示 AM1808 — Sitara 处理器: Arm9，LPDDR，DDR2，显示，以太网 AM1810 — Sitara 处理器: Arm9，LPDDR，DDR2，显示，以太网，PROFIBUS AM4377 — Sitara 处理器：Arm Cortex-A9、PRU-ICSS、EtherCAT AM4378 — Sitara 处理器：Arm Cortex-A9、PRU-ICSS、3D 图形
软件
软件开发套件 (SDK)
PRU-SWPKG — 可编程实时单元 (PRU) 软件支持包
下载选项
软件开发套件 (SDK)

WINCESDK-AM1XOMAPL1X — 用于 Sitara™ ARM® AM1x /OMAP-L1x 器件的 Windows 嵌入式 CE ™ 软件开发套件 (SDK)

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Microsoft Windows™ 嵌入式 CE* (CE) 6.0 R3 这款操作系统专门针对需要最小存储器（基于组合架构）的嵌入式器件进行了优化。Windows CE 是具有显著特点的内核，它可以在低于 1 兆字节的存储器中运行。它符合实时操作系统的定义，具有确定的中断延迟。专为与 Microsoft 的 Platform Builder 和 Visual Studio 工具配合使用而设计，Windows 嵌入式 CE 6.0 R3 操作系统使开发人员能够使用熟悉的全功能嵌入式设计环境来立即着手开发。通过使用熟悉的标准 Windows 嵌入式 CE 应用编程接口 (...)
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驱动程序或库

STARTERWARE-AM18X — 针对 AM18x 处理器的 StarterWare

StarterWare provides C-based no-OS platform support for TI's ARM9™ and ARM® Cortex™ A8 based devices. StarterWare provides device abstraction layer libraries, peripheral programming examples such as Ethernet, graphics and USB, and board level example applications. StarterWare can be (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
基于 Arm 的处理器
AM1806 — Sitara 处理器: Arm9，LPDDR，DDR2，显示
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驱动程序或库

STARTERWARE-AM335X — 针对 AM335x 处理器的 StarterWare

StarterWare provides C-based no-OS platform support for TI's ARM9™ and ARM® Cortex™ A8 based devices. StarterWare provides device abstraction layer libraries, peripheral programming examples such as Ethernet, graphics and USB, and board level example applications. StarterWare can be (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
基于 Arm 的处理器
AM1806 — Sitara 处理器: Arm9，LPDDR，DDR2，显示
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IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

此设计资源支持这些类别中的大部分米6体育平台手机版_好二三四。

查看米6体育平台手机版_好二三四详情页，验证是否能提供支持。
启动 下载选项
操作系统 (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
来源：Mentor Graphics Corporation
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支持软件

SPRC940.ZIP — PRU Software Development Package [XP]

The PRU Software Support Package is an add-on package that provides a framework and examples for developing software for the Programmable Real-time Unit sub-system and Industrial Communication Sub-System (PRU-ICSS) in the supported TI processors.  The PRU-ICSS achieves deterministic, real-time (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
基于 Arm 的处理器
AM1806 — Sitara 处理器: Arm9，LPDDR，DDR2，显示 AM1810 — Sitara 处理器: Arm9，LPDDR，DDR2，显示，以太网，PROFIBUS
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仿真模型

AM1806 ZCE BSDL

SPRM482.ZIP (8 KB) - BSDL Model
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仿真模型

AM1806 ZCE IBIS Model (Rev. A)

SPRM483A.ZIP (120 KB) - IBIS Model
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仿真模型

AM1806 ZWT BSDL Model

SPRM484.ZIP (8 KB) - BSDL Model
下载
仿真模型

AM1806 ZWT IBIS Model (Rev. A)

SPRM485A.ZIP (121 KB) - IBIS Model
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封装 引脚 CAD 符号、封装和 3D 模型
NFBGA (ZCE) 361 Ultra Librarian
NFBGA (ZWT) 361 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

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