DAC8812 Dual, Serial-Input 16-Bit Multiplying Digital-to-Analog Converter

1 Features

Relative Accuracy: 1 LSB Max
Differential Nonlinearity: 1 LSB Max
2-mA Full-Scale Current ±20%,
With V_REF = ±10 V
0.5-μs Settling Time
Midscale or Zero-Scale Reset
Separate 4Q Multiplying Reference Inputs
Reference Bandwidth: 10 MHz
Reference Dynamics: –105-dB THD
SPI™-Compatible 3-Wire Interface:
50 MHz
Double Buffered Registers to Enable
Simultaneous Multichannel Update
Internal Power-On Reset
Industry-Standard Pin Configuration

2 Applications

Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration

3 Description

The DAC8812 is a dual, 16-bit, current-output digital-to-analog converter (DAC) designed to operate from a single 2.7-V to 5.5-V supply.

The applied external reference input voltage V_REF determines the full-scale output current. An internal feedback resistor (R_FB) provides temperature tracking for the full-scale output when combined with an external I-to-V precision amplifier.

A double-buffered, serial data interface offers high-speed, 3-wire, SPI and microcontroller compatible inputs using serial data in (SDI), clock (CLK), and a chip-select (CS). A common level-sensitive load DAC strobe (LDAC) input allows simultaneous update of all DAC outputs from previously loaded input registers. Additionally, an internal power-on reset forces the output voltage to zero at system turnon. An MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0, or to midscale code when MSB = 1.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DAC8812	TSSOP (16)	5.00 mm × 4.40 mm

For all available packages, see the orderable addendum at the end of the data sheet.

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Functional Block Diagram

4 Revision History

Changes from E Revision (March 2016) to F Revision

Changed the maximum T_A value from 125°C to 85°C in the Recommended Operating Conditions table Go
Changed the name of the input resistance match parameter to Channel-to-channel input resistance match in the Electrical Characteristics tableGo
Made V_REF negative in the equation for V_OUTGo
Added the Receiving Notification of Documentation Updates section Go

Changes from D Revision (January 2016) to E Revision

Changed the DAC8812 Timing Diagram imageGo

Changes from C Revision (November 2015) to D Revision

Changed the DAC8812 Timing Diagram image to show the setup and hold time with respect to rising edge Go

Changes from B Revision (February 2007) to C Revision

Added ESD Ratings table, Timing Requirements and Switching Characteristics tables, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
Replaced Package/Ordering Information table with Device Comparison tableGo
Added I/O column to Pin Functions tableGo

5 Device Comparison Table

DEVICE	MAXIMUM RELATIVE ACCURACY (LSB)
DAC8812C	±1
DAC8812B	±2

6 Pin Configuration and Functions

PW Package

16-Pin TSSOP

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	R_FBA	I	Establish voltage output for DAC A by connecting to external amplifier output.
2	V_REFA	I	DAC A reference voltage input pin. Establishes DAC A full-scale output voltage. Can be tied to V_DD pin.
3	I_OUTA	O	DAC A current output
4	A_GNDA	—	DAC A analog ground
5	A_GNDB	—	DAC B analog ground
6	I_OUTB	O	DAC B current output
7	V_REFB	I	DAC B reference voltage input pin. Establishes DAC B full-scale output voltage. Can be tied to V_DD pin.
8	R_FBB	I	Establish voltage output for DAC B by connecting to external amplifier output.
9	SDI	I	Serial data input; data loads directly into the shift register.
10	RS	I	Reset pin; active-low input. Input registers and DAC registers are set to all 0s or midscale. Register data = 0x0000 when MSB = 0. Register data = 0x8000 when MSB = 1 for DAC8812.
11	CS	I	Chip-select; active-low input. Disables shift register loading when high. Transfers serial register data to input register when CS goes high. Does not affect LDAC operation.
12	DGND	—	Digital ground
13	V_DD	I	Positive power-supply input. Specified range of operation 2.7 V to 5.5 V.
14	MSB	I	MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can be permanently tied to ground or V_DD.
15	LDAC	I	Load DAC register strobe; level-sensitive active-low. Transfers all input register data to the DAC registers. Asynchronous active-low input. See Table 2 for operation.
16	CLK	I	Clock input. Positive edge clocks data into shift register.

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
V_DD to GND	–0.3	7	V
V_REFx, R_FBx to GND	–18	18	V
Digital logic inputs to GND	–0.3	V_DD + 0.3	V
I_OUTx to GND	–0.3	V_DD + 0.3	V
A_GNDx to DGND	–0.3	0.3	V
Input current to any pin except supplies	–50	50	mA
Package power dissipation		(T_Jmax – T_A) / R_θJA	W
Maximum junction temperature (T_Jmax)		150	°C
Operating temperature	–40	85	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±4000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_DD	Supply voltage to GND	2.7		5.5	V
T_A	Operating ambient temperature	–40		85	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		DAC8812	UNIT
		PW (TSSOP)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	100.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	32.8	°C/W
R_θJB	Junction-to-board thermal resistance	46.8	°C/W
ψ_JT	Junction-to-top characterization parameter	2	°C/W
ψ_JB	Junction-to-board characterization parameter	46	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

V_DD = 2.7 V to 5.5 V, I_OUTX = Virtual GND, A_GNDX = 0 V, V_REFA,B = 10 V, T_A = full operating temperature range, unless otherwise noted.

PARAMETER		CONDITIONS	MIN	TYP	MAX	UNIT
STATIC PERFORMANCE⁽¹⁾
	Resolution				16	Bits
INL	Relative accuracy	DAC8812B			±2	LSB
INL	Relative accuracy	DAC8812C			±1	LSB
DNL	Differential nonlinearity				±1	LSB
I_OUTx	Output leakage current	Data = 0000h, T_A = 25°C			10	nA
I_OUTx	Output leakage current	Data = 0000h, T_A = T_A max			20	nA
G_FSE	Full-scale gain error	Data = FFFFh		±0.75	±4	mV
TCV_FS	Full-scale temperature coefficient⁽²⁾			1		ppm/°C
R_FBX	Feedback resistor	V_DD = 5 V		5		kΩ
REFERENCE INPUT⁽²⁾
V_REFx	V_REFx range		–15		15	V
R_REFx	Input resistance		4	5	6	kΩ
	Channel-to-channel input resistance match			1%
C_REFx	Input capacitance			5		pF
ANALOG OUTPUT⁽²⁾
I_OUTx	Output current	Data = FFFFh	1.6		2.5	mA
C_OUTx	Output capacitance	Code-dependent		50		pF
LOGIC INPUTS⁽²⁾
V_IL	Input low voltage	V_DD = 2.7 V			0.6	V
V_IL	Input low voltage	V_DD = 5 V			0.8	V
V_IH	Input high voltage	V_DD = 2.7 V	2.1			V
V_IH	Input high voltage	V_DD = 5 V	2.4			V
I_IL	Input leakage current				1	μA
C_IL	Input capacitance				10	pF
SUPPLY CHARACTERISTICS
V_{DD RANGE}	Power supply range		2.7		5.5	V
I_DD	Positive supply current	Logic inputs = 0 V, V_DD = 4.5 V to 5.5 V		2	5	μA
I_DD	Positive supply current	Logic inputs = 0 V, V_DD = 2.7 V to 3.6 V		1	2.5	μA
P_DISS	Power dissipation	Logic inputs = 0 V			0.0275	mW
P_SS	Power supply sensitivity	ΔV_DD = ±5%			0.006%
AC CHARACTERISTICS⁽²⁾ ⁽³⁾
t_s	Output voltage settling time	To ±0.1% of full-scale, Data = 0000h to FFFFh to 0000h		0.3		µs
t_s	Output voltage settling time	To ±0.0015% of full-scale, Data = 0000h to FFFFh to 0000h		0.5		µs
Q_G	DAC glitch impulse	Data = 7FFFh to 8000h to 7FFFh		5		nV-s
BW –3 dB	Reference multiplying BW	V_REFx = 100 mV_RMS, Data = FFFFh, C_FB = 3 pF		10		MHz
	Feedthrough error	Data = 0000h, V_REFx = 100 mV_RMS, f = 100 kHz		–70		dB
	Crosstalk error	Data = 0000h, V_REFB = 100 mV_RMS, Adjacent channel, f = 100 kHz		–100		dB
Q_D	Digital feedthrough	CS = 1 and f_CLK = 1 MHz		1		nV-s
THD	Total harmonic distortion	V_REF = 5 V_PP, Data = FFFFh, f = 1 kHz		–105		dB
e_n	Output spot noise voltage	f = 1 kHz, BW = 1 Hz		12		nV/√Hz

(1) All static performance tests (except I_OUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter amplifier. The DAC8812 R_FB pin is tied to the amplifier output. Typical values represent average readings measured at 25°C.

(2) These parameters are not subject to production testing.

(3) All ac characteristic tests are performed in a closed-loop system using a THS4011 I-to-V converter amplifier.

7.6 Timing Requirements

See Figure 1

		MIN	UNIT
INTERFACE TIMING⁽¹⁾
t_CH	Clock duration, high	10	ns
t_CL	Clock duration, low	10	ns
t_CSS	CS to clock setup	0	ns
t_CSH	Clock to CS hold	10	ns
t_LDAC	Load DAC pulse duration	20	ns
t_DS	Data setup	10	ns
t_DH	Data hold	10	ns
t_LDS	Load setup	5	ns
t_LDH	Load hold	25	ns