DLPC3433 和 DLPC3438 显示控制器

1 特性

2 应用

3 说明

DLPC3433 或 DLPC3438 数字控制器均属于 DLP3010 (0.3 720p) 芯片组的一部分，用于支持 DLP3010 数字微镜装置 (DMD) 的可靠运转。DLPC3433 或 DLPC3438 控制器在系统电子设备与 DMD 之间提供一个方便的多功能接口，从而实现了小外形尺寸的低功耗高分辨率 HD 显示屏。

访问 TI DLP®Pico™ 显示技术入门页面，并查看编程人员指南了解详情。

该芯片组提供现成的资源，可帮助用户加快设计周期。这些资源包括可直接用于生产环境的光学模块、光学模块制造商和设计公司。

器件信息⁽¹⁾⁽²⁾

器件型号	封装	封装尺寸（标称值）
DLPC3433	NFBGA (176)	7.00mm × 7.00mm
DLPC3438	NFBGA (201)	13.00mm × 13.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购米6体育平台手机版_好二三四附录。

(2) DSI 仅适用于 DLPC3433。DSI 不适用于 DLPC3438。

典型简化系统图

4 Revision History

Changes from Revision D (June 2019) to Revision E (November 2020)

• 更新了整个文档中的表格、图和交叉参考的编号格式Go
• 总数据表格式和订购更新Go
• 将像素时钟规格上限更改为 155MHzGo
• 向支持的 PMIC 添加了 DLPA3005 并添加了指向 PMIC 米6体育平台手机版_好二三四文件夹的链接Go
• Changed layout of pinout maps to improve readability for user.Go
• Deleted mention of mirror parking time from PARKZ pin description and moved to a specification tableGo
• Changed JTAG pin names from reserved to proper names Go
• Deleted support for adjustable DATAEN_CMD polarity Go
• Deleted mention of a specific 3D command Go
• Deleted support for adjusting PCLK capture edge in software Go
• Changed the description of how to use the CMP_OUT pin and corrected how the comparator must use GPIO_10 (RC_CHARGE) instead of CMP_PWM Go
• Deleted support for CMP_PWMGo
• Added note about VCC_INTF power up recommendations if secondary devices are on the I²C bus Go
• Deleted mention of unsupported keypad inputs Go
• Corrected optional MTR_SENSE support to GPIO_18 instead of GPIO_19 Go
• Deleted mention of unsupported light sensor on GPIO_13 and GPIO_12 Go
• Deleted reference of the RC_CHARGE circuit being used for the light sensor and added reference of it being used for the thermistor Go
• Deleted reference of the LS_PWR circuit being used for the light sensorGo
• Deleted mention of the unsupported LABB output sample and hold sensor control signalGo
• Clarified GPIO_03 - GPIO_01 pins are required to be used as a SPI1 portGo
• Deleted misleading note about GPIO pins defaulting to inputs Go
• Corrected how pins are mentioned that are only available on the DLPC3438Go
• Added missing I/O definition 10 Go
• Deleted unneeded VCC_INTF and VCC_FLSH absolute maximum values Go
• Added high voltage tolerant note to Absolute Maximum Ratings table Go
• Changed incorrect pin tolerance Go
• Changed Power Electrical Characteristics table to reflect updated power measurement values and techniques Go
• Added note that the power numbers vary depending on the utilized softwareGo
• Changed and fixed incorrect test conditions for current drive strengthsGo
• Deleted redundant ǀV_ODǀ specification which is referenced in later sectionsGo
• Added minimum and maximum values for V_OH for I/O type 4Go
• Added minimum and maximum values for V_OL for I/O type 4Go
• Deleted incorrect reference to 2.5-V, 24-mA drive Go
• Corrected I²C buffer test conditionsGo
• Deleted incorrect steady-state common mode voltage reference Go
• Changed high voltage tolerant I/O note to only refer to the I²C buffer and changed VCC to VCC_INTF.Go
• Added |V_OD| minimum and maximum values, and changed the typical valueGo
• Added high-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted redundant mention of specification, and changed the typical value Go
• Added low-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted redundant mention of specification, and changed the typical value Go
• Corrected the name of the DMD Low-Speed signals from inputs to outputs Go
• Deleted V_OH(DC) maximum and V_OL(DC) minimum valuesGo
• Added note about DMD input specs being met if a proper series termination resistor is used Go
• Deleted reference of selecting unsupported oscillator frequency Go
• Corrected system oscillator clock period to match clock frequency Go
• Changed pulse duration percent spec from a maximum to a minimum Go
• Added condition for VDD rise time Go
• Deleted the incorrect part of the t_{p_tvb} definitionGo
• Deleted unneeded total horizontal blanking equation Go
• Changed minimum total vertical blanking equation Go
• Increased maximum PCLK from 150 MHz to 155 MHz Go
• Deleted reference to various signal's active edges being configurable Go
• Changed the minimum flash SPI_CLK frequencyGo
• Corrected flash interface clock period to match clock frequency Go
• Added Section 6.17 section to more clearly list signal transition time requirementsGo
• Changed GPIO_08 (PROJ_ON) pulse width requirement and added a requirement to keep GPIO_08 high until HOST_IRQ goes low Go
• Changed DMD HS clock switching rate from maximum to nominal and added accompanying clock specification Go
• Added Section 6.19 sectionGo
• Added the Section 6.20 section to clarify chipset support requirementsGo
• Changed how chipset support is mentioned in the Detailed Description section Go
• Deleted support for 3D video over DSI Go
• Deleted reference to internal software tools and clarified how firmware affects the supported resolution and frame rates Go
• Added note stating bits per pixel limitation at 120 Hz with DSI inputGo
• Added note that up to four DSI lanes may be required to fully utilize the bandwidth Go
• Deleted mention of sequencer sync mode as its generally assumed to be autoGo
• Clarified note about VSYNC_WE needing to remain active Go
• Deleted support for changing the clock active edge and clarified support of changing the sync active edgeGo
• Changed the DATAEN_CMD signal to not be optional Go
• Added note that LP mode is required during vertical time for DSI Go
• Changed requirement related to DSI initialization Go
• Deleted incorrect DSI data type; see software programmers guide instead.Go
• Added information that the parallel interface isn't ready to accept data until the auto-initialization process is completedGo
• Changed how the 500 ms startup time is described Go
• Changed SPI flash key timing parameter access frequency minimum and maximum valuesGo
• Changed maximum flash size supported from 16 Mb to 128 Mb Go
• Deleted SPI signal routing section Go
• Deleted support for a light sensor integrated with the DLPC34xx controller Go
• Added missing timing definitions Go
• Clarified that the mentioned SDR clock speed is the typical valueGo
• Changed the description of how PROJ_ON affects the power supplies Go
• Changed which signals are listed as tri-stated at power up and which signals are pulled low Go
• Changed 1-oz copper plane recommendation Go
• Deleted reference to unsupported option of variable frequency reference clockGo
• Added additional DMD data and DMD clock signal matching requirements Go
• Changed maximum mismatch from ±0.1" to ±1.0" Go
• Changed incorrect signal matching requirement table noteGo
• Changed differential signal layer change to a recommendationGo
• Changed wording requiring no more than two vias on certain DMD signals Go
• Changed the package designator description for the DLPC3433 to match the actual packageGo
• Changed device markings image and definitions Go