TPD2S701-Q1 汽车类 USB 双通道数据线路 VBUS 短路保护和 IEC ESD 保护
- ZHCSGF6A April 2017 – July 2017 TPD2S701-Q1
  
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TPD2S701-Q1 汽车类 USB 双通道数据线路 VBUS 短路保护和 IEC ESD 保护

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1 特性

符合 AEC-Q100 标准
- –40°C 至 125°C 的工作温度范围
VD+ 和 VD– 上的 VBUS 短路保护
ESD 性能 VD+，VD–
- ±8kV 接触放电（IEC 61000-4-2 和 ISO 10605 330pF，330Ω）
- ±15kV 气隙放电（IEC 61000-4-2 和 ISO 10605 330pF，330Ω）
高速数据开关（1GHz 带宽）
只需要 5V 电源
可调节 OVP 阈值
快速过压响应时间（典型值 200ns）
热关断特性
集成输入使能和故障输出信号
保证数据完整性的直通路由
- 10 引脚 VSSOP 封装 (3mm × 3mm)
- 10 引脚 QFN 封装 (2.5mm × 2.5mm)

2 应用

终端设备
- 音响主机
- 后座娱乐系统
- 远程信息处理
- USB 集线器
- 导航模块
- 媒体接口
接口
- USB 2.0
- USB 3.0

3 说明

TPD2S701-Q1 是一款用于汽车高速接口（如 USB 2.0）的双通道线路 V_BUS 短路和 IEC61000-4-2 ESD 保护器件。TPD2S701-Q1 包含两个数据线路 nFET 开关。这些开关通过提供业界一流的带宽，实现最小的信号衰减，同时可保护内部系统电路（在 VD+ 和 VD– 引脚上），使其免受过压情况的损坏，从而确保安全的数据通信。

在这些引脚上，此器件可实现直流电高达 7V 的过压保护。这为 USB V_BUS 轨的数据线路短路提供了充分保护。该过压保护电路提供业界最可靠的 V_BUS 短路隔离，能在 200ns 内关闭数据开关，并保护上游电路免受有害电压和电流尖峰影响。

此外，TPD2S701-Q1 只需要 5V 的单一电源，这优化了电源树的大小和成本。该器件允许通过电阻分压器网络调整 OVP 阈值和钳位电路，为优化系统保护提供了一种简单且经济高效的方法（适用于任何收发器）。TPD2S701-Q1 还包括一个 FLT 引脚，该引脚会在器件出现过压状况时发出指示，并在过压状况消除后自动复位。

TPD2S701-Q1 还在 VD+ 和 VD– 引脚上集成了系统级别的 IEC 61000-4-2 和 ISO 10605 ESD 钳位，因此在应用中无需再配置高压、低电容的外部 TVS 钳位电路。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
TPD2S701-Q1	VSSOP (10)	3.00mm × 3.00mm
TPD2S701-Q1	QFN (10)	2.50mm x 2.50mm

要了解所有可用封装，请参见米6体育平台手机版_好二三四说明书末尾的可订购米6体育平台手机版_好二三四附录。

功能框图

4 修订历史

Changes from * Revision (April 2017) to A Revision

Updated Figure 19 Go

5 Pin Configuration and Functions

DGS Package

10-Pin SSOP

Top View

DSK Package

10-Pin QFN

Top View

Pin Functions

PIN		TYPE	DESCRIPTION
NO.	NAME	TYPE	DESCRIPTION
1	VD–	I/O	High voltage D– USB data line, connect to USB connector D+, D– IEC61000-4-2 ESD protection
2	VD+	I/O	High voltage D+ USB data line, connect to USB connector D+, D– IEC61000-4-2 ESD protection
3	GND	Ground	Ground pin for internal circuits and IEC ESD clamps
4	FLT	O	Open-drain fault pin. See Table 1
5	EN	I	Enable active-low input. Drive EN low to enable the switches. Drive EN high to disable the switches. See Table 1 for mode selection
6	MODE	I	Selects between device modes. See the Detailed Description section. Acts as LDO reference voltage for mode 1
7	VPWR	I	5-V DC supply input for internal circuits. Connect to internal power rail on PCB
8	VREF	I/O	Pin to set OVP threshold. See the Detailed Description section for instructions on how to set OVP threshold
9	D+	I/O	I/O protected low voltage D+ USB data line, connects to transceiver
10	D–	I/O	Protected low voltage D– USB data line, connects to transceiver

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾ ⁽²⁾

		MIN	MAX	UNIT
V_PWR	5-V DC supply voltage for internal circuitry	–0.3	7.7	V
V_REF	Pin to set OVP threshold	–0.3	6	V
VD+, VD–	Voltage range from connector-side USB data lines	–0.3	7.7	V
D+, D–	Voltage range for internal USB data lines	–0.3	V_REF + 0.3	V
V_MODE	Voltage on MODE pin	–0.3	7.7	V
V_FLT	Voltage on FLT pin	–0.3	7.7	V
V_EN	Voltage on enable pin	–0.3	7.7	V
T_A	Operating free air temperature⁽³⁾	–40	125	°C
T_STG	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(3) Thermal limits and power dissipation limits must be observed.

6.2 ESD Ratings—AEC Specification

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	All pins	±2000	V
		Charged-device model (CDM), per AEC Q100-011	All pins besides corners	±500
		Charged-device model (CDM), per AEC Q100-011	Corner pins	±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings—IEC Specification

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 contact discharge	VD+, VD– pins⁽¹⁾	±8000	V
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 air-gap discharge	VD+, VD– pins⁽¹⁾	±15000	V

(1) See Figure 19 for details on system level ESD testing setup.

6.4 ESD Ratings—ISO Specification

				VALUE	UNIT
V_ESD ⁽¹⁾	Electrostatic discharge	ISO 10605 (330 pF, 330 Ω) contact discharge (10 strikes)	VD+, VD– pins	±8000	V
		ISO 10605 (330 pF, 330 Ω) air-gap discharge (10 strikes)	VD+, VD– pins	±15000
		ISO 10605 (150 pF, 330 Ω) contact discharge (10 strikes)	VD+, VD– pins	±8000
		ISO 10605 (150 pF, 330 Ω) air-gap discharge (10 strikes)	VD+, VD– pins	±15000
		ISO 10605 (330 pF, 2 kΩ) contact discharge (10 stikes)⁽²⁾	VD+, VD– pins	±8000
		ISO 10605 (330 pF, 2 kΩ) air-gap discharge (10 strikes)	VD+, VD– pins	±15000
		ISO 10605 (150 pF, 2 kΩ) air-gap discharge (10 discharges)	VD+, VD– pins	±25000

(1) See Figure 19 for details on system level ESD testing setup.

(2) VREF > 3 V.

6.5 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	TYP	MAX	UNIT
V_PWR	5-V DC supply voltage for internal circuitry		4.5		7	V
V_REF	Mode 0. Voltage range for V_REF pin (for setting OVP threshold)		3		3.6	V
V_REF	Mode 1. Voltage range for V_REF pin (for setting OVP threshold)		0.63		3.8	V
VD+, VD–	Voltage range from connector-side USB data lines		0		3.6	V
D+, D–	Voltage range for internal USB data lines		0		3.6	V
V_EN	Voltage range for enable		0		7	V
V_FLT	Voltage range for FLT		0		7	V
I_FLT	Current into open drain FLT pin FET		0		3	mA
C_VPWR	V_PWR capacitance⁽¹⁾	External Capacitor on V_PWR pin	1	10		µF
C_VREF	V_REF capacitance	External Capacitor on V_REF pin	0.3	1	3	µF
C_MODE	Allowed parasitic capacitance on mode pin from PCB and mode 1 external resistors				20	pF
R_{MODE_0}	Resistance to GND to set to mode 0			2	2.6	kΩ
R_{MODE_1}	Resistance to GND to set to mode 1 (calculate parallel combination of R_TOP and R_BOT)		14	20		kΩ

(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin. Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature variation. The effective value presented should be within the minimum and maximums listed in the table.

6.6 Thermal Information

THERMAL METRIC⁽¹⁾		TPD2S701-Q1		UNIT
		DGS (VSSOP)	DSK (WSON)
		10 PINS	10 PINS
θ_JA	Junction-to-ambient thermal resistance	167.3	61.5	°C/W
θ_JCtop	Junction-to-case (top) thermal resistance	56.9	51.3	°C/W
θ_JB	Junction-to-board thermal resistance	87.6	34	°C/W
ψ_JT	Junction-to-top characterization parameter	7.7	1.3	°C/W
ψ_JB	Junction-to-board characterization parameter	86.2	34.3	°C/W
θ_JCbot	Junction-to-case (bottom) thermal resistance	N/A	7.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
MODE 1 ADJUSTABLE V_REF
V_{MODE_CMP}	Mode 1 V_REF feedback regulator voltage	V_MODE	Standard mode 1 set-up. EN = 0 V. Once V_REF = 3.3 V, measure voltage on mode pin	0.47	0.5	0.53	V
I_{MODE_LEAK}	Mode pin mode 1 leakage current	I_MODE	Standard mode 1. Remove RTOP and RBOT. Power up device and wait until start-up time has passed. Then force 0.53 V on the MODE pin and measure current into pin		50	200	nA
V_{REF_ACCURACY}	V_REF accuracy	V_REF	Informative, test parameters below; accuracy with R_TOP and R_BOT as ±1% resistors	–8%		8%
V_{REF_3.3V}	Mode 1 VREF set to 3.3 V	V_REF	Standard mode 1 set-up. R_TOP = 140 kΩ ± 1%, R_BOT = 24.9 kΩ ± 1%. EN = 0. Measure value of V_REF once it settles	3.04	3.31	3.58	V
V_{REF_0.66V}	Mode 1 V_REF set to 0.66 V	V_REF	Standard mode 1 set-up. R_TOP = 47.5 kΩ ± 1%, R_BOT = 150 kΩ ± 1%.EN = 0. Measure value of V_REF once it settles	0.6	0.66	0.72	V
V_{REF_3.8V}	Mode 1 V_REF set to 3.8 V	V_REF	Standard mode 1 set-up. R_TOP = 165 kΩ ± 1%, R_BOT = 24.9 kΩ ± 1%. EN = 0. Measure value of V_REF once it settles	3.5	3.81	4.12	V
EN, FLT PINS
V_IH	High-level input voltage	EN	Mode 0. Connect VPWR = 5 V; V_REF = 3.3 V; VD+ = 3.3 V; Set VIH(EN) = 0 V; Sweep VIH from 0 V to 1.4 V; Measure when D+ drops low (less than or equal to 5% of 3.3 V) from 3.3 V	1.2			V
V_IH	Low-level input voltage	EN	Mode 0. Connect VPWR = 5 V; V_REF = 3.3 V; VD+ = 3.3 V. Set VIH(EN) = 3.3 V; Sweep VIH from 3.3 V to 0.5 V; Measure when D+ rise to 95% of 3.3 V from 0 V			0.8	V
I_IL	Input leakage current	EN	Mode 0. VPWR = 5 V; V_REF = 3.3 V; VI (EN) = 3.3 V ; Measure current into EN pin			1	µA
V_OL	Low-level output voltage	FLT	Mode 0. Drive the TPS2S701-Q1 in OVP to assert FLT pin. Source I_OL = 1 mA into FLT pin and measure voltage on FLT pin when asserted			0.4	V
T_{SD_RISING}	The rising over temperature protection shutdown threshold		VPWR = 5 V, ENZ = 0 V, T_A stepped up until FLTZ is asserted	140	150	165	℃
T_{SD_FALLING}	The falling over temperature protection shutdown threshold		VPWR = 5 V, ENZ = 0 V, T_A stepped down from T_{SD_RISING} until FLTZ is cleared	125	138	150	℃
T_{SD_HYST}	The over temperature protection shutdown threshold hysteresis		T_{SD_RISING} – T_{SD_FALLING}	10	12	15	℃
OVP CIRCUIT—VD±
V_{OVP_RISING}	Input overvoltage protection threshold, V_REF > 3.6 V	VD±	Mode 1. Set V_PWR = 5 V; EN = 0 V; R_TOP = 165 kΩ, R_BOT = 24.9 kΩ. Connect D± to 40-Ω load. Increase VD+ or VD– from 4.1 V to 4.9 V. Measure the value at which FLTZ is asserted	4.3	4.5	4.7	V
V_{OVP_RISING}	Input overvoltage protection threshold	VD±	Mode 1. Set V_PWR = 5 V; EN = 0 V; R_TOP = 140 kΩ, R_BOT = 24.9 kΩ. Increase VD+ or VD– from 3.6 V to 4.6 V. Measure the value at which FLTZ is asserted. Repeat for R_TOP = 39 kΩ, R_BOT = 150 kΩ. Increase VD+ or VD– from 0.6 V to 0.9 V. Measure the value at which FLTZ is asserted. See the resultant values meet the equation, and make sure to observe data switches turnoff. Also check for mode 0 when V_REF = 3.3 V	1.19 × V_REF	1.25 × V_REF	1.31 × V_REF	V
V_{HYS_OVP}	Hysteresis on OVP	VD±	Difference between rising and falling OVP thresholds on VD±		25		mV
V_{OVP_FALLING}	Input overvoltage protection threshold	VD±	After collecting each rising OVP threshold, lower the VD± voltage until you see FLT deassert. This gives the falling OVP threshold. Use this value to calculate V_{HYS_OVP}		VOVP_RISING – VHYS_OVP		V
I_{VD_LEAK_0 V}	Leakage current on VD± during normal operation	VD±	Standard mode 0 or mode 1. Set VD± = 0 V. D± = floating. Measure current flowing into VD±	–0.1		0.1	µA
I_{VD_LEAK_3.6V}	Leakage current on VD± during normal operation	VD±	Standard mode 0 or mode 1. Set VD± = 3.6 V. D± = floating. Measure current flowing into VD±		2.5	4	µA
V_{OVP_3.3V}	Input overvoltage threshold for VREF = 3.3 V	VD±	Standard mode 1. R_TOP = 140 kΩ ± 1%, R_BOT = 24.9 kΩ ± 1%. Connect D± to 40-Ω load. Measure the value at which FLTZ is asserted	3.61	4.14	4.67	V
V_{OVP_0.66V}	Input overvoltage threshold for VREF = 0.66 V	VD±	Standard mode 1. R_TOP = 47.5 kΩ ± 1%, R_BOT = 150 kΩ ± 1%. Connect D± to 40-Ω load. Measure the value at which FLTZ is asserted	0.72	0.83	0.94	V
DATA LINE SWITCHES – VD+ to D+ or VD– to D–
R_ON	On resistance		Mode 0 or 1. Set V_PWR = 5 V; V_REF = 3.3 V; EN = 0 V; Measure resistance between D+ and VD+ or D– and VD–, voltage between 0 and 0.4 V		4	6.5	Ω
R_ON(Flat)	On resistance flatness		Mode 0 or 1. Set V_PWR = 5 V; V_REF = 3.3 V; EN = 0 V; Measure resistance between D+ and VD+ or D– and VD–, sweep voltage between 0 and 0.4 V. Take difference of resistance at 0.4-V and 0-V VD± bias			1	Ω
BW_ON	On bandwidth (–3-dB)		Mode 0 or 1. Set V_PWR = 5 V; V_REF = 3.3 V; EN = 0 V; Measure S21 bandwidth from D+ to VD+ or D– to VD– with voltage swing = 400 mVpp, Vcm = 0.2 V		960		MHz

6.8 Power Supply and Supply Current Consumption Chracteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_{UVLO_RISING_VPWR}	V_PWR rising UVLO threshold	Use standard mode 0 set-up. Set EN = 0 V, load D+ to 45 Ω, VD+ = 3.3 V. Set V_PWR = 3.5 V, and step up V_PWR until 90% of VD+ appears on D+	3.7	3.95	4.2	V
V_{UVLO_HYST_VPWR}	VPWR UVLO hysteresis	Use standard mode 0 set up. Set EN = 0 V, load D+ to 45 Ω, VD+ = 3.3 V. Set V_PWR = 4.3 V, and step down V_PWR until D+ falls to 10% of VD+. This gives V_{UVLO_FALLING_VPWR}. V_{UVLO_RISING_VPWR} – V_{UVLO_FALLING_VPWR} = V_{UVLO_HYST_VPWR} for this unit	250	300	400	mV
V_{UVLO_RISING_VREF}	VREF rising UVLO threshold in mode 0	Use standard mode 0 set up. Set EN = 0V, load D+ to 45 Ω, VD+ = 3.3 V. Set VREF = 2.5 V, and step up VREF until 90% of VD+ appears on D+	2.6	2.7	2.9	V
V_{UVLO_HYST_VREF}	VREF UVLO hysteresis	Use standard mode 0 set up. Set EN = 0 V, load D+ to 45 Ω, VD+ = 3.3 V. Set VREF = 3 V, and step down VREF until D+ falls to 10% of VD+. This gives V_{UVLO_FALLING_VREF}. V_{UVLO_RISING_VREF} –V_{UVLO_FALLING_VREF} = V_{UVLO_HYST_VREF} for this unit	75	125	200	mV
I_{VPWR_DISABLED_MODE0}	V_PWR disabled current consumption	Use standard mode 0. EN = 5 V . Measure current into V_PWR			110	µA
I_{VPWR_DISABLED_MODE1}	V_PWR disabled current consumption	Use standard mode 1. EN = 5 V. Measure current into V_PWR			110	µA
I_{VREF_DISABLED}	VREF disabled current consumption mode 0	Use standard mode 0. EN = 5 V. Measure current into VREF			10	µA
I_{VPWR_MODE0}	V_PWR pperating current consumption	Use standard mode 0. EN = 0 V. Measure current into V_PWR			250	µA
I_{VPWR_MODE1}	V_PWR operating current consumption	Use standard mode 1. EN = 0 V. Measure current into V_PWR			350	µA
I_VREF	VREF operating current consumption mode 0	Use standard mode 0. EN = 0 V. Measure current into V_REF		12	20	µA
I_{CHG_VREF}	VREF fast charge current	Standard mode 1. 0.1 µF < C_VREF < 3 µF. Set-up for charging to 3.3 V. Use a high voltage capacitor that does not derate capacitance up the 3.3 V. Measure slope to calculate the current when C_VREF cap is being charged. Test to check this OPEN LOOP method		22		mA
I_{D_OFF_LEAK_STB}		Mode 0. Measured flowing into D+ or D– supply, V_PWR = 0 V, VD+ or VD– = 18 V, EN = 0 V, V_REF = 0 V, D± = 0 V	–1		1	µA
I_{D_ON_LEAK_STB}		Mode 0. Measured flowing into D+ or D– supply, V_PWR = 5 V, VD+ or VD– = 18 V, EN = 0 V, V_REF = 3.3 V, D± = 0 V	–1		1	µA
I_{VD_OFF_LEAK_STB}		Mode 0. Measured flowing out of VD+ or VD– supply, V_PWR = 0 V, VD+ or VD– = 18 V, EN = 0 V, V_REF = 0 V, D± = 0 V			120	µA
I_{VD_ON_LEAK_STB}		Mode 0. Measured flowing out of VD+ or VD– supply, V_PWR = 5 V, VD+ or VD– = 18 V, EN = 0 V, V_REF = 3.3 V, D± = 0 V			120	µA
I_{VPWR_TO_VREF_LEAK}	Leakage from VPWR to VREF	Use standard mode 0. Set VREF = 0 V. Measured current flowing out of VREF pin			1	µA
I_{VREF_TO_VPWR_LEAK}	Leakage from VREF to VPWR	Use standard mode 0. Set VPWR = 0 V. Measured as current flowing out of VPWR pin			1	µA

6.9 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
ENABLE PIN AND VREF FAST CHARGE
T_{VREF_CHG}	VREF fast charge time	Time between when 5 V is applied to V_PWR, and V_REF reaches V_{VREF_FAST_CHG}. Needs to happen before or at same time t_{ON_STARTUP} completes		0.5	1	ms
T_{ON_STARTUP_MODE0}	Device turnon time from UVLO mode 0	Mode 0. EN = 0 V, measured from V_PWR and V_REF = UVLO⁺ to data FET ON, V_PWRcomes to UVLO⁺ second. Place 3.3 V on VD±. Ramp VREF to 3.3 V, then VPWR to 5 V and measure the time it takes for D± to reach 90% of VD±		0.5	1	ms
T_{ON_STARTUP_MODE1}	Device turnon time from UVLO mode 1	Informative. mode 1. EN = 0 V, measured from V_PWR = UVLO⁺ to data FET ON		0.5 + T_{CHG_CVREF}		ms
T_{ON_STARTUP_MODE1_3.3V}	Device turnon time from UVLO mode 1	Mode 1. EN = 0 V, measured from V_PWR = UVLO⁺ to data FET ON, C_VREF = 1 µF, V_{REF_FINAL} = 3.3 V. Measure the time it takes for D± to reach 90% of VD±		0.6	1	ms
T_{ON_EN_MODE0}	Device turnon time mode 0	Mode 0. V_PWR = 5 V, V_REF= 3.3 V, time from EN is asserted until data FET is ON. Place 3.3 V on VD±, measure the time it takes for D± to reach 90% of VD±		150		µs
T_{ON_EN_MODE1}	Device turnon time mode 1	Mode 1. V_PWR = 5 V, V_{REF_INITIAL} = 0 V, time from EN is asserted until data FET is ON. Place 3.3 V on VD±, measure the time it takes for D± to reach 90% of VD±		150 + T_{CHG_VREF}		µs
T_{ON_EN_MODE1_3.3V}	Device turnon time mode 1 for VREF = 3.3 V	Mode 1. V_PWR = 5 V, V_{REF_INITIAL} = 0 V, time from EN is asserted until data FET is ON. Place 3.3 V on VD±, measure the time it takes for D± to reach 90% of VD±. C_VREF = 1 µF, VREF_FINAL = 3.3 V		300		µs
T_{OFF_EN}	Device turnoff time	Mode 0 or 1. V_PWR = 5 V, V_REF = 3.3 V, time from EN is deasserted until data FET is off. Place 3.3 V on VD±, measure the time it takes for D± to fall to 10% of VD±, R_D± = 45 Ω		5		µs
T_{CHG_CVREF}	Time to charge C_VREF	Informative. Mode 1. Time from V_REF = 0 V to 80% × V_{REF_FINAL} after EN transitions from high to low		(C_VREF × 0.8 (V_{REF_FINAL})/(I_{CHG_VREF})		s
T_{CHG_CVREF_3.3V}	Time to charge C_VREF to 3.3 V	Mode 1. Time from V_REF = 0 V to 90% × 3.3 V after EN transitions from high to low, C_VREF = 1 µF		132		µs
T_{CHG_CVREF_0.66V}	Time to charge C_VREF to 0.66 V	Mode 1. Time from V_REF = 0 V to 90% × 0.63 V after EN transitions from high to low, C_VREF = 1 µF. R_TOP = 47.5 kΩ ± 1%, R_BOT = 150 kΩ ± 1%		26		µs
OVERVOLTAGE PROTECTION
t_{OVP_response_VBUS}	OVP response time to VBUS	Mode 0 or 1. Measured from OVP condition to FET turn off . Short VD± to 5 V and measure the time it takes D± voltage to reach 0.1 × V_{D±_CLAMP_MAX} from the time the 5-V hot-plug is applied. R_{LOAD_D±} = 45 Ω.⁽¹⁾ ⁽²⁾		2		µs
t_{OVP_response}	OVP response time	Mode 0 or 1. Measured from OVP condition to FET turn off . Short VD± to 18 V and measure the time it takes D± voltage to reach 0.1 × V_{D±_CLAMP_MAX}from the time the 18-V hot-plug is applied. R_{LOAD_D±} = 45 Ω⁽¹⁾ ⁽²⁾		0.1	1	µs
t_{OVP_Recov} _{_FLT}	Recovery time FLT pin	Measured from OVP clear to FLT deassertion⁽¹⁾		32		ms
t_{OVP_Recov} _{_FET}	Recovery time for data FET to turn back on	Measured from OVP clear until FET turns back on. Drop VD+ from 16 V to 3.3 V with V_REF = 3.3 V, measure time it takes for D+ to reach 90% of 3.3 V		32		ms
t_{OVP_ASSERT}	FLT assertion time	Measured from OVP on VD+ or VD– to FLT assertion	12.6	18	23.4	ms