TPS51200-EP 灌/拉 DDR 终端稳压器
- ZHCSF57 June 2016 TPS51200-EP
  
  PRODUCTION DATA.

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TPS51200-EP 灌/拉 DDR 终端稳压器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

输入电压：支持 2.5V 和 3.3V 电源轨
VLDOIN 电压范围：1.1V 至 3.5V
具有压降补偿功能的灌电流和拉电流终端稳压器
所需最小输出电容为 20μF（通常为 3 × 10μF MLCC），用于存储器终端应用 (DDR)
用于监视输出稳压的 PGOOD
EN 输入
REFIN 输入允许直接或通过电阻分压器灵活进行输入跟踪
远程感测 (VOSNS)
±10mA 缓冲基准 (REFOUT)
内置软启动，欠压锁定 (UVLO) 和过流限制 (OCL)
热关断
符合 DDR 和 DDR2 JEDEC 规范
支持 DDR3、低功耗 DDR3 和 DDR4 VTT 应用
带有散热焊盘的 10 引脚超薄小外形尺寸无引线 (VSON) 封装
支持国防、航天和医疗应用
- 受控基线
- 一个组装和测试场所
- 一个制造场所
- 支持军用温度范围（-55°C 至 125°C）
- 延长的米6体育平台手机版_好二三四使用寿命周期
- 延长的米6体育平台手机版_好二三四变更通知
- 米6体育平台手机版_好二三四可追溯性

2 应用范围

用于 DDR、DDR2、DDR3、低功耗 DDR3 和 DDR4 的存储器终端稳压器
笔记本、台式机和服务器
电信和数据通信
基站
液晶 (LCD) 电视和等离子 (PDP) 电视
复印机和打印机
机顶盒

3 说明

TPS51200-EP 器件是一款灌电流和拉电流双倍数据速率 (DDR) 终端稳压器，专用于空间问题是重要考量因素的低输入电压、低成本、低噪声系统。

TPS51200-EP 能够保持快速瞬态响应，最低仅需 20μF 输出电容。TPS51200-EP 支持远程感测功能并且可满足 DDR、DDR2、DDR3、低功耗 DDR3 和 DDR4 VTT 总线的所有电源要求。

此外，TPS51200-EP 还提供一个开漏 PGOOD 信号监测输出稳压，提供一个 EN 信号在 S3（挂起至 RA4M）期间针对 DDR 进行 VTT 放电。

TPS51200-EP 采用带散热焊盘的高效散热型 10 引脚超薄小外形尺寸无引线 (VSON) 封装，无铅且绿色环保。其额定工作温度范围为 -55°C 至 +125°C。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
TPS51200-EP	VSON (10)	3.00mm x 3.00mm

要了解所有可用封装，请见数据表末尾的可订购米6体育平台手机版_好二三四附录。

简化的 DDR 应用

4 修订历史记录

日期	修订版本	注释
2016 年 6 月	*	最初发布。

5 Pin Configuration and Functions

DRC Package

10-Pin VSON With Exposed Thermal Pad

Top View

Pin Functions

PIN		I/O⁽²⁾	DESCRIPTION
NAME	NO.	I/O⁽²⁾	DESCRIPTION
EN	7	I	For DDR VTT application, connect EN to SLP_S3. For any other application, use the EN pin as the ON/OFF function.
GND	8	G	Signal ground. Connect to negative terminal of the output capacitor.
PGND⁽¹⁾	4	G	Power ground output for the LDO.
PGOOD	9	O	PGOOD output. Indicates regulation.
REFIN	1	I	Reference input.
REFOUT	6	O	Reference output. Connect to GND through 0.1-μF ceramic capacitor.
VIN	10	I	2.5-V or 3.3-V power supply. A ceramic decoupling capacitor with a value between 1-μF and 4.7-μF is required.
VLDOIN	2	I	Supply voltage for the LDO.
VO	3	O	Power output for the LDO.
VOSNS	5	I	Voltage sense input for the LDO. Connect to positive terminal of the output capacitor or the load.

(1) Thermal pad connection. See Figure 31 in the Thermal Design Considerations section for additional information.

(2) I = Input, O = Output, G = Ground.

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Input voltage⁽²⁾	REFIN, VIN, VLDOIN, VOSNS	–0.3	3.6	V
	EN	–0.3	6.5
	PGND to GND	–0.3	0.3
Output voltage⁽²⁾	REFOUT, VO	–0.3	3.6	V
Output voltage⁽²⁾	PGOOD	–0.3	6.5	V
Operating junction temperature, T_J		–55	150	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply voltages	VIN	2.375	3.5	V
Voltage	EN, VLDOIN, VOSNS	–0.1	3.5	V
	REFIN	0.5	1.8
	PGOOD, VO	–0.1	3.5
	REFOUT	–0.1	1.8
	PGND	–0.1	0.1
Operating junction temperature, T_J		–55	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS51200-EP	UNIT
		DRC (VSON)
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	55.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	84.6	°C/W
R_θJB	Junction-to-board thermal resistance	30	°C/W
ψ_JT	Junction-to-top characterization parameter	5.5	°C/W
ψ_JB	Junction-to-board characterization parameter	30.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	10.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over recommended junction temperature range, V_VIN = 3.3 V, V_VLDOIN = 1.8 V, V_REFIN = 0.9 V, V_VOSNS = 0.9 V, V_EN = V_VIN, C_OUT = 3 × 10 μF and circuit shown in (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENT
I_IN	Supply current	T_J = 25 °C, V_EN = 3.3 V, no load		0.7	1	mA
I_IN(SDN)	Shutdown current	T_J = 25 °C, V_EN = 0 V, V_REFIN = 0, no load		65	80	μA
I_IN(SDN)	Shutdown current	T_J = 25 °C, V_EN = 0 V, V_REFIN > 0.4 V, no load		200	400	μA
I_LDOIN	Supply current of VLDOIN	T_J = 25 °C, V_EN = 3.3 V, no load		1	50	μA
I_LDOIN(SDN)	Shutdown current of VLDOIN	T_J = 25 °C, V_EN = 0 V, no load		0.1	50	μA
INPUT CURRENT
I_REFIN	Input current, REFIN	V_EN = 3.3 V			1	μA
VO OUTPUT
V_VOSNS	Output DC voltage, VO	V_REFOUT = 1.25 V (DDR1), I_O = 0 A		1.25		V
		V_REFOUT = 1.25 V (DDR1), I_O = 0 A	–15		15	mV
		V_REFOUT = 0.9 V (DDR2), I_O = 0 A		0.9		V
		V_REFOUT = 0.9 V (DDR2), I_O = 0 A	–15		15	mV
		V_LDOIN = 1.5 V, V_REFOUT = 0.75 V (DDR3), I_O = 0 A		0.75		V
		V_LDOIN = 1.5 V, V_REFOUT = 0.75 V (DDR3), I_O = 0 A	–15		15	mV
V_VOTOL	Output voltage tolerance to REFOUT	–2 A < I_VO < 2 A	–25		25	mV
I_VOSRCL	VO source current Limit	With reference to REFOUT, V_OSNS = 90% × V_REFOUT	3		4.5	A
I_VOSNCL	VO sink current Limit	With reference to REFOUT, V_OSNS = 110% × V_REFOUT	3.5		5.5	A
I_DSCHRG	Discharge current, VO	V_REFIN = 0 V, V_VO = 0.3 V, V_EN = 0 V, T_J = 25°C		18	25	Ω
POWERGOOD COMPARATOR
V_TH(PG)	VO PGOOD threshold	PGOOD window lower threshold with respect to REFOUT	–23.5%	–20%	–17.5%
		PGOOD window upper threshold with respect to REFOUT	17.5%	20%	23.5%
		PGOOD hysteresis		5%
t_PGSTUPDLY	PGOOD start-up delay	Start-up rising edge, VOSNS within 15% of REFOUT		2		ms
V_PGOODLOW	Output low voltage	I_SINK = 4 mA			0.4	V
t_PBADDLY	PGOOD bad delay	VOSNS is outside of the ±20% PGOOD window		10		μs
I_PGOODLK	Leakage current⁽¹⁾	V_OSNS = V_REFIN (PGOOD high impedance), V_PGOOD = V_VIN + 0.2 V			1	μA
REFIN AND REFOUT
V_REFIN	REFIN voltage range		0.5		1.8	V
V_REFINUVLO	REFIN undervoltage lockout	REFIN rising	360	390	420	mV
V_REFINUVHYS	REFIN undervoltage lockout hysteresis			20		mV
V_REFOUT	REFOUT voltage			REFIN		V
V_REFOUTTOL	REFOUT voltage tolerance to V_REFIN	–10 mA < I_REFOUT < 10 mA, V_REFIN = 1.25 V	–15		15	mV
		–10 mA < I_REFOUT < 10 mA, V_VREFIN = 0.9 V	–15		15
		–10 mA < I_REFOUT < 10 mA, V_REFIN = 0.75 V	–15		15
		–10 mA < I_REFOUT < 10 mA, V_REFIN = 0.6 V	–15		15
I_REFOUTSRCL	REFOUT source current limit	V_REFOUT = 0 V	10	40		mA
I_REFOUTSNCL	REFOUT sink current limit	V_REFOUT = 0 V	10	40		mA
UVLO AND EN LOGIC THRESHOLD
V_VINUVVIN	UVLO threshold	Wake up, T_J = 25°C	2.2	2.3	2.375	V
V_VINUVVIN	UVLO threshold	Hysteresis		50		mV
V_ENIH	High-level input voltage	Enable	1.7			V
V_ENIL	Low-level input voltage	Enable			0.3	V
V_ENYST	Hysteresis voltage	Enable		0.5		V
I_ENLEAK	Logic input leakage current	EN, T_J = 25°C	–1		1	μA
THERMAL SHUTDOWN
T_SON	Thermal shutdown threshold⁽¹⁾	Shutdown temperature		150		°C
T_SON	Thermal shutdown threshold⁽¹⁾	Hysteresis		25		°C

(1) Ensured by design. Not production tested.

1. Electromigration fail mode = time at temperature with bias.

2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).

3. The predicted operating lifetime versus junction temperature is based on reliability modeling and available qualification data.

Figure 1. Predicted Lifetime Derating Chart for TPS51200-EP

6.6 Typical Characteristics

3 × 10-µF MLCCs (0805) are used on the output.

V_VIN = 3.3 V

DDR

Figure 2. Load Regulation

V_VIN = 3.3 V

DDR3

Figure 4. Load Regulation

V_VIN = 2.5 V

DDR

Figure 6. Load Regulation

V_VIN = 2.5 V

DDR3

Figure 8. Load Regulation

DDR

Figure 10. REFOUT Load Regulation

DDR3

Figure 12. REFOUT Load Regulation

Figure 14. DROPOUT Voltage vs Output Current

DDR3

Figure 16. Bode Plot

V_VIN = 3.3 V

DDR2

Figure 3. Load Regulation

V_VIN = 3.3 V

LP DDR3 or DDR4

Figure 5. Load Regulation

V_VIN = 2.5 V

DDR2

Figure 7. Load Regulation

V_VIN = 2.5 V

LP DDR3 or DDR4

Figure 9. Load Regulation

DDR2

Figure 11. REFOUT Load Regulation

LP DDR3 or DDR4

Figure 13. REFOUT Load Regulation

DDR2

Figure 15. Bode Plot

7 Detailed Description

7.1 Overview

The TPS51200-EP device is a sink and source double data rate (DDR) termination regulator specifically designed for low-input voltage, low-cost, low-noise systems where space is a key consideration.

The device maintains a fast transient response and only requires a minimum output capacitance of 20 μF. The device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, Low-Power DDR3, and DDR4 VTT bus termination.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Sink and Source Regulator (VO Pin)

The TPS51200-EP is a sink and source tracking termination regulator specifically designed for low-input voltage, low-cost, and low-external component count systems where space is a key application parameter. The device integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcing and sinking current. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be used to support the fast load transient response. To achieve tight regulation with minimum effect of trace resistance, connect a remote sensing terminal, VOSNS, to the positive terminal of each output capacitor as a separate trace from the high-current path from VO.

7.3.2 Reference Input (REFIN Pin)

The output voltage, VO, is regulated to REFOUT. When REFIN is configured for standard DDR termination applications, REFIN can be set by an external equivalent ratio voltage divider connected to the memory supply bus (VDDQ). The TPS51200-EP device supports REFIN voltages from 0.5 V to 1.8 V, making it versatile and ideal for many types of low-power LDO applications.

7.3.3 Reference Output (REFOUT Pin)

When it is configured for DDR termination applications, REFOUT generates the DDR VTT reference voltage for the memory application. It is capable of supporting both a sourcing and sinking load of 10 mA. REFOUT becomes active when REFIN voltage rises to 0.39 V and VIN is above the UVLO threshold. When REFOUT is less than 0.375 V, it is disabled and subsequently discharges to GND through an internal 10-kΩ MOSFET. REFOUT is independent of the EN pin state.

7.3.4 Soft-Start Sequencing

A current clamp implements the soft-start function of the VO pin. The current clamp allows the output capacitors to be charged with low and constant current, providing a linear ramp-up of the output voltage. When VO is outside of the powergood (PGOOD) window, the current clamp level is one-half of the full overcurrent limit (OCL) level. When VO rises or falls within the PGOOD window, the current clamp level switches to the full OCL level. The soft-start function is completely symmetrical and the overcurrent limit works for both directions. The soft-start function works not only from GND to the REFOUT voltage, but also from VLDOIN to the REFOUT voltage.

7.3.5 Enable Control (EN Pin)

When EN is driven high, the VO regulator begins normal operation. When the device drives EN low, VO discharges to GND through an internal 18-Ω MOSFET. REFOUT remains on when the device drives EN low. Ensure that the EN pin voltage remains lower than or equal to V_VIN at all times.

7.3.6 Powergood Function (PGOOD Pin)

The TPS51200-EP device provides an open-drain PGOOD output that goes high when the VO output is within ±20% of REFOUT. PGOOD de-asserts within 10 μs after the output exceeds the size of the PGOOD window. During initial VO start-up, PGOOD asserts high 2 ms (typ) after the VO enters PGOOD window. Because PGOOD is an open-drain output, a pull-up resistor with a value between 1 kΩ and 100 kΩ, placed between PGOOD and a stable active supply voltage rail, is required.

7.3.7 Current Protection (VO Pin)

The LDO has a constant overcurrent limit (OCL). The OCL level reduces by one-half when the output voltage is not within the PGOOD window. This reduction is a non-latch protection.

7.3.8 UVLO Protection (VIN Pin)

For VIN undervoltage lockout (UVLO) protection, the TPS51200-EP monitors VIN voltage. When the VIN voltage is lower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown is a non-latch protection.

7.3.9 Thermal Shutdown

The TPS51200-EP monitors junction temperature. If the device junction temperature exceeds the threshold value, (typically 150°C), the VO and REFOUT regulators both shut off, discharged by the internal discharge MOSFETs. This shutdown is a non-latch protection.

7.3.10 Tracking Start-up and Shutdown

The TPS51200-EP also supports tracking start-up and shutdown when the EN pin is tied directly to the system bus and not used to turn on or turn off the device. During tracking start-up, VO follows REFOUT once REFIN voltage is greater than 0.39 V. REFIN follows the rise of VDDQ rail through a voltage divider. The typical soft-start time (t_SS) for the VDDQ rail is approximately 3 ms, however it may vary depending on the system configuration. The soft-start time of the VO output no longer depends on the OCL setting, but it is a function of the soft-start time of the VDDQ rail. PGOOD is asserted 2 ms after V_VO is within ±20% of REFOUT. During tracking shutdown, the VO pin voltage falls following REFOUT until REFOUT reaches 0.37 V. When REFOUT falls below 0.37 V, the internal discharge MOSFETs turn on and quickly discharge both REFOUT and VO to GND. PGOOD is deasserted once VO is beyond the ±20% range of REFOUT. Figure 18 shows the typical timing diagram for an application that uses tracking start-up and shutdown.

Figure 17. Typical Timing Diagram for S3 and Pseudo-S5 Support

Figure 18. Typical Timing Diagram of Tracking Start-up and Shutdown

7.4 Device Functional Modes

7.4.1 Low-Input Voltage Applications

TPS51200-EP can be used in an application system that offers either a 2.5-V rail or a 3.3-V rail. If only a 5-V rail is available, consider using the TPS51100 device as an alternative. The TPS51200-EP device has a minimum input voltage requirement of 2.375 V. If a 2.5-V rail is used, ensure that the absolute minimum voltage (both DC and transient) at the device pin is be 2.375 V or greater. The voltage tolerance for a 2.5-V rail input is between –5% and 5% accuracy, or better.

7.4.2 S3 and Pseudo-S5 Support

The TPS51200-EP provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal in the end application. Both REFOUT and VO are on when EN = high (S0 state). REFOUT is maintained while VO is turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). When EN = low and the REFIN voltage is less than 0.39 V, TPS51200-EP enters pseudo-S5 state. Both VO and REFOUT outputs are turned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged (S4 or S5 state). Figure 17 shows a typical start-up and shutdown timing diagram for an application that uses S3 and pseudo-S5 support.