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CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs
SCAS862G
November 2008 – July 2016
CDCE62005
PRODUCTION DATA.
CONTENTS
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CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Thermal Information
6.4
Electrical Characteristics
6.5
Timing Requirements
6.6
SPI Bus Timing Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagrams
8.2.1
Interface and Control Block
8.2.2
Input Block
8.2.3
Output Block
8.2.4
Clock Divider Module 0-4
8.2.5
Synthesizer Block
8.2.6
Computing The Output Frequency
8.3
Feature Description
8.3.1
Phase Noise Analysis
8.3.2
Output To Output Isolation
8.3.3
Device Control
8.3.4
External Control Pins
8.3.5
Input Block
8.3.5.1
Universal Input Buffers (UIB)
8.3.5.2
LVDS Fail Safe Mode
8.3.5.3
Smart Multiplexer Controls
8.3.5.4
Smart Multiplexer Auto Mode
8.3.5.5
Smart Multiplexer Dividers
8.3.5.6
Output Block
8.3.5.7
Output Multiplexer Control
8.3.5.8
Output Buffer Control
8.3.5.9
Output Buffer Control - LVCMOS Configurations
8.3.5.10
Output Dividers
8.3.5.11
Digital Phase Adjust
8.3.5.12
Phase Adjust Example
8.3.5.13
Valid Register Settings for Digital Phase Adjust Blocks
8.3.5.14
Output Synchronization
8.3.5.15
Auxiliary Output
8.3.5.16
Synthesizer Block
8.3.5.17
Input Divider
8.3.5.18
Feedback and Feedback Bypass Divider
8.3.5.18.1
VCO Select
8.3.5.18.2
Prescaler
8.3.5.18.3
Charge Pump Current Settings
8.3.5.18.4
Loop Filter
8.3.5.19
Internal Loop Filter Component Configuration
8.3.5.20
External Loop Filter Component Configuration
8.3.6
Digital Lock Detect
8.3.7
Crystal Input Interference
8.3.8
VCO Calibration
8.3.9
Startup Time Estimation
8.3.10
Analog Lock Detect
8.4
Device Functional Modes
8.4.1
Fan-Out Buffer
8.4.2
Clock Generator
8.4.3
Jitter Cleaner - Mixed Mode
8.4.3.1
Clocking ADCs with the CDCE62005
8.4.3.2
CDCE62005 SERDES Startup Mode
8.5
Programming
8.5.1
Interface and Control Block
8.5.1.1
Serial Peripheral Interface (SPI)
8.5.1.2
CDCE62005 SPI Command Structure
8.5.1.3
SPI Interface Master
8.5.1.4
SPI Consecutive Read/Write Cycles to the CDCE62005
8.5.1.5
Writing to the CDCE62005
8.5.1.6
Reading from the CDCE62005
8.5.1.7
Writing to EEPROM
8.5.2
Device Configuration
8.6
Register Maps
8.6.1
Device Registers: Register 0 Address 0x00
8.6.2
Device Registers: Register 1 Address 0x01
8.6.3
Device Registers: Register 2 Address 0x02
8.6.4
Device Registers: Register 3 Address 0x03
8.6.5
Device Registers: Register 4 Address 0x04
8.6.6
Device Registers: Register 5 Address 0x05
8.6.7
Device Registers: Register 6 Address 0x06
8.6.8
Device Registers: Register 7 Address 0x07
8.6.9
Device Registers: Register 8 Address 0x08
9
Application and Implementation
9.1
Application Information
9.1.1
Frequency Synthesizer
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Trademarks
12.2
Documentation Support
12.3
Electrostatic Discharge Caution
12.4
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
パッケージ・オプション
メカニカル・データ（パッケージ｜ピン）
RGZ|48
MPQF123F
サーマルパッド・メカニカル・データ
RGZ|48
QFND131R
発注情報
scas862g_oa
scas862g_pm
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