CD54HC112

ACTIVE

High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger

Product details

Number of channels 2 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 20 Supply current (max) (µA) 80 IOL (max) (mA) -6 IOH (max) (mA) 6 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 20 Supply current (max) (µA) 80 IOL (max) (mA) -6 IOH (max) (mA) 6 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
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* Data sheet CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger datasheet (Rev. J) PDF | HTML 14 Oct 2022

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