Product details

Technology family LVC Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 6 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Military Operating temperature range (°C) -55 to 125
Technology family LVC Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 6 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 14 130.4652 mm² 19.56 x 6.67 CFP (W) 14 58.023 mm² 9.21 x 6.3 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model (A114-A)
    • 200-V machine model (A115-A)
    • 1000-V charged-device model (C101)
  • Operate from 1.65 V to 3.6 V VCC
  • Specified from –40°C to +85°C, –40°C to 125°C, and –55°C to 125°C
  • Inputs accept voltages to 5.5 V
  • Max tpd of 6.4 ns at 3.3 V
  • Typical VOLP (output ground bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model (A114-A)
    • 200-V machine model (A115-A)
    • 1000-V charged-device model (C101)
  • Operate from 1.65 V to 3.6 V VCC
  • Specified from –40°C to +85°C, –40°C to 125°C, and –55°C to 125°C
  • Inputs accept voltages to 5.5 V
  • Max tpd of 6.4 ns at 3.3 V
  • Typical VOLP (output ground bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

The SN54LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC14A hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V VCC operation.

The devices contain six independent inverters and perform the Boolean function Y = A.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V or 5-V system environment.

The SN54LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC14A hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V VCC operation.

The devices contain six independent inverters and perform the Boolean function Y = A.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V or 5-V system environment.

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Technical documentation

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Type Title Date
* Data sheet SNx4LVC14A Hex Schmitt-Trigger Inverters datasheet (Rev. AC) PDF | HTML 20 Apr 2022
* SMD SN54LVC14A SMD 5962-97615 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
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User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
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Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
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Application note LVC Characterization Information 01 Dec 1996
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Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

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Package Pins CAD symbols, footprints & 3D models
CDIP (J) 14 Ultra Librarian
CFP (W) 14 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

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