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SN74AUP2G08

ACTIVE

2-ch, 2-input 0.8-V to 3.6-V low power (< 1uA) AND gate

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Data sheet

SN74AUP2G08

ACTIVE
Data sheet Order now

Product details

Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 2 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 2 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YFP) 8 1.8 mm² 1 x 1.8 DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 UQFN (RSE) 8 2.25 mm² 1.5 x 1.5 VSSOP (DCU) 8 6.2 mm² 2 x 3.1 X2SON (DQE) 8 1.4 mm² 1.4 x 1
  • Wide operating VCC range of 0.8V to 3.6V
  • Low static-power consumption (ICC = 0.9µA max)
  • Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports partial-power-down mode operation
  • Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
  • 3.6V I/O tolerant to support mixed-mode signal operation
  • tpd = 5.9ns max at 3.3V
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • Wide operating VCC range of 0.8V to 3.6V
  • Low static-power consumption (ICC = 0.9µA max)
  • Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports partial-power-down mode operation
  • Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
  • 3.6V I/O tolerant to support mixed-mode signal operation
  • tpd = 5.9ns max at 3.3V
  • Latch-up performance exceeds 100mA per JESD 78, Class II

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when VCC = 0V, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when VCC = 0V, preventing damaging current backflow through the device when it is powered down.
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Technical documentation

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Type Title Date
* Data sheet SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate datasheet (Rev. E) PDF | HTML 29 Apr 2024
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 May 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004

Design & development

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Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
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Simulation model

SN74AUP2G08 Behavioral SPICE Model

SCEM678.ZIP (7 KB) - PSpice Model
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Many TI reference designs include the SN74AUP2G08

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DSBGA (YFP) 8 Ultra Librarian
DSBGA (YZP) 8 Ultra Librarian
UQFN (RSE) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
X2SON (DQE) 8 Ultra Librarian
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