The SN74HCS237 is a three to eight decoder with latched address inputs, one standard output strobe (G0), and one active low output strobe (G 1). When the latch enable (LE) input is low, the device acts as a standard three to eight decoder. When the latch enable (LE) input is high, the address latch retains its previous state. When the outputs are gated by either strobe input, they are all forced into the low state. When the outputs are not disabled by one or both of the strobe inputs, only the selected output is high while all others are low.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | SN74HCS237 3- to 8-Line Decoder/Demultiplexer with Address Latches and Schmitt-Trigger Inputs datasheet (Rev. A) | PDF | HTML | 16 Jun 2021 |
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The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
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