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Noninverting buffers & drivers

SN74LVC3G17

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3-ch, 1.65-V to 5.5-V buffers with Schmitt-Trigger inputs

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Data sheet

SN74LVC3G17

ACTIVE
Data sheet Order now

Product details

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 3 IOL (max) (mA) 32 Supply current (max) (µA) 10 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 3 IOL (max) (mA) 32 Supply current (max) (µA) 10 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Maximum tpd of 5.4 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Maximum tpd of 5.4 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This triple Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC3G17 device contains three buffers and performs the Boolean function Y = A. The device functions as three independent buffers but, because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT) signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This triple Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC3G17 device contains three buffers and performs the Boolean function Y = A. The device functions as three independent buffers but, because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT) signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
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Technical documentation

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Type Title Date
* Data sheet SN74LVC3G17 Triple Schmitt-Trigger Buffer datasheet (Rev. F) PDF | HTML 31 Aug 2015
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 May 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

SN74LVC3G17 Behavioral SPICE Model

SCEM602.ZIP (7 KB) - PSpice Model
Download
Simulation model

SN74LVC3G17 IBIS Model (Rev. A)

SCEM364A.ZIP (45 KB) - IBIS Model
Download
Reference designs

TIDA-00178 — Interface to a Sin/Cos Encoder with Sitara AM437x Reference Design

The TIDA-00178 reference design is an EMC compliant industrial interface to Sin/Cos position encoders. Applications include industrial drives, which require accurate speed and position control.

The design utilizes a 16-bit dual sample ADC with drop-in compatible 14- or 12-bit versions available, (...)


Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
DSBGA (YZP) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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