SN74LVCZ161284A

Name: SN74LVCZ161284A
Brand: TI
SKU: SN74LVCZ161284A
Price: 0.381 USD

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19-Bit IEEE 1284 Std Bus Interface

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Data sheet

document-pdfAcrobat SN74LVCZ161284A,19-Bit IEEE1284 Translation Transceiver With Error-Free Power-Up datasheet (Rev. B)

SN74LVCZ161284A

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Data sheet

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Product details

Technology family

LVC

Applications

IEEE1284

Rating

Catalog

Operating temperature range (°C)

0 to 70

Technology family

LVC

Applications

IEEE1284

Rating

Catalog

Operating temperature range (°C)

0 to 70

TSSOP (DGG)

48

101.25 mm² 12.5 x 8.1

Power-On Reset (POR) Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at Pins A9–A13
Operates From 3 V to 3.6 V
1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
Designed for the IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
Flow-Through Architecture Optimizes PCB Layout
I_off and Power-Up 3-State Support Hot Insertion
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 4000-V Human-Body Model (A114-A)
- 350-V Machine Model (A115-A)
- 1500-V Charged-Device Model (C101)

Power-On Reset (POR) Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at Pins A9–A13
Operates From 3 V to 3.6 V
1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
Designed for the IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
Flow-Through Architecture Optimizes PCB Layout
I_off and Power-Up 3-State Support Hot Insertion
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 4000-V Human-Body Model (A114-A)
- 350-V Machine Model (A115-A)
- 1500-V Charged-Device Model (C101)

The SN74LVCZ161284A is designed for 3-V to 3.6-V V_CC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high, and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side, and four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above V_CC CABLE. If V_CC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. V_CC is designed for 3-V to 3.6-V operation. V_CC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when V_CC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The Power-On Reset (POR) ensures that the Y outputs (Y9–Y13) stay in the high state after power on until an associated input (A9–A13) goes high. When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer system errors caused by deasserting the BUSY signal in the cable at power on.

The SN74LVCZ161284A is designed for 3-V to 3.6-V V_CC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high, and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side, and four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above V_CC CABLE. If V_CC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. V_CC is designed for 3-V to 3.6-V operation. V_CC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when V_CC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The Power-On Reset (POR) ensures that the Y outputs (Y9–Y13) stay in the high state after power on until an associated input (A9–A13) goes high. When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer system errors caused by deasserting the BUSY signal in the cable at power on.

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