Home Interface I2C & I3C ICs I2C & I3C level shifters, buffers & hubs
Home
Interface
I2C & I3C ICs
I2C & I3C level shifters, buffers & hubs

TCA9416

ACTIVE

Ultra-low voltage I2C translator with rise time accelerators

Order now
Data sheet

TCA9416

ACTIVE
Data sheet Order now

Product details

Features Output Enable Protocols I2C Frequency (max) (MHz) 1 VCCA (min) (V) 1.08 VCCA (max) (V) 3.6 VCCB (min) (V) 1.08 VCCB (max) (V) 3.6 Supply restrictions No rule Rating Catalog Operating temperature range (°C) -40 to 125
Features Output Enable Protocols I2C Frequency (max) (MHz) 1 VCCA (min) (V) 1.08 VCCA (max) (V) 3.6 VCCB (min) (V) 1.08 VCCB (max) (V) 3.6 Supply restrictions No rule Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23-THN (DDF) 8 8.12 mm² 2.9 x 2.8 X2SON (DTM) 8 1.08 mm² 0.8 x 1.35
  • 2-bit bidirectional translator for SDA and SCL lines in I2C applications
  • Provides bidirectional voltage translation with no direction pin
  • High-impedance output SCL_A, SDA_A, SCL_B, SDA_B pins when OE = 0 V or VCC = 0 V
  • Internal 10-kΩ pull-up resistor on all SDA and SCL pins are enabled based on respective VCC voltage
  • 1.08 V to 3.6 V on both A and B ports
  • VCC Isolation feature: If either VCC input is at GND, both ports are in the high-impedance state (excluding pull-ups)
  • No power-supply sequencing required: either VCCA or VCCB can be ramped first
  • Low Ioff of 2.5 µA when either VCCA or VCCB = 0 V
  • OE input can be tied directly to VCCA or controlled by GPIO
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD Protection exceeds JESD 22
    • 2500-V Human-body model (A114-B)
    • 1500-V Charged-device model (C101)
  • 2-bit bidirectional translator for SDA and SCL lines in I2C applications
  • Provides bidirectional voltage translation with no direction pin
  • High-impedance output SCL_A, SDA_A, SCL_B, SDA_B pins when OE = 0 V or VCC = 0 V
  • Internal 10-kΩ pull-up resistor on all SDA and SCL pins are enabled based on respective VCC voltage
  • 1.08 V to 3.6 V on both A and B ports
  • VCC Isolation feature: If either VCC input is at GND, both ports are in the high-impedance state (excluding pull-ups)
  • No power-supply sequencing required: either VCCA or VCCB can be ramped first
  • Low Ioff of 2.5 µA when either VCCA or VCCB = 0 V
  • OE input can be tied directly to VCCA or controlled by GPIO
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD Protection exceeds JESD 22
    • 2500-V Human-body model (A114-B)
    • 1500-V Charged-device model (C101)

The TCA9416 is a 2-bit bidirectional I2C and SMBus voltage-level translator with an output enable (OE) input and rising and falling edge accelerators. It is operational from 1.08 V to 3.6 V on both the A-side and B-side. This allows the device to interface between lower and higher logic signal levels at any of the typical 1.2-V, 1.8-V, 2.5-V, and 3.3-V supply rails.

The OE input pin is referenced to VCCA, can be tied directly to VCCA, but it is also 3.6-V tolerant. The OE pin can also be controlled and set to a logic low to place all the SCL and SDA pins in a high-impedance state, which significantly reduces the quiescent current consumption.

Under normal I2C and SMBus configurations, the TCA9416 is compatible with standard speeds where the frequency of SCL is 100 kHz (Standard-mode), 400 kHz (Fast-mode), or 1 MHz (Fast-mode Plus).

The TCA9416 features internal 10-kΩ pull-up resistors on SCL_A, SDA_A, SCL_B, and SDA_B. Additional external pull-up resistors can be added to the bus to reduce the total pull-up resistance and speed up rising edges.

The TCA9416 is a 2-bit bidirectional I2C and SMBus voltage-level translator with an output enable (OE) input and rising and falling edge accelerators. It is operational from 1.08 V to 3.6 V on both the A-side and B-side. This allows the device to interface between lower and higher logic signal levels at any of the typical 1.2-V, 1.8-V, 2.5-V, and 3.3-V supply rails.

The OE input pin is referenced to VCCA, can be tied directly to VCCA, but it is also 3.6-V tolerant. The OE pin can also be controlled and set to a logic low to place all the SCL and SDA pins in a high-impedance state, which significantly reduces the quiescent current consumption.

Under normal I2C and SMBus configurations, the TCA9416 is compatible with standard speeds where the frequency of SCL is 100 kHz (Standard-mode), 400 kHz (Fast-mode), or 1 MHz (Fast-mode Plus).

The TCA9416 features internal 10-kΩ pull-up resistors on SCL_A, SDA_A, SCL_B, and SDA_B. Additional external pull-up resistors can be added to the bus to reduce the total pull-up resistance and speed up rising edges.
filter Find other I2C & I3C level shifters, buffers & hubs
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 4
Type Title Date
* Data sheet TCA9416 Ultra-Low-Voltage I2C Translator with Rise Time Accelerators datasheet (Rev. A) PDF | HTML 06 Aug 2021
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024
EVM User's guide TCA9416 Evaluation Module PDF | HTML 08 Mar 2021
Certificate TCA9416EVM EU Declaration of Conformity (DoC) 25 Feb 2021

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TCA9416EVM — TCA9416 ultra-low voltage I2C translator with rise time accelerators evaluation module

This EVM provides configurable loading conditions through adjustable pull up resistors and bus capacitance which allows designers to easily test the performance of this device in their system.

User guide: PDF | HTML
Not available on TI.com
Simulation model

TCA9416 IBIS Model

SCPM047.ZIP (63 KB) - IBIS Model
Download
Design tool

I2C-DESIGNER — I2C designer tool

Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard (...)
Evaluate in the cloud
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
View Options
Package Pins CAD symbols, footprints & 3D models
SOT-23-THN (DDF) 8 Ultra Librarian
X2SON (DTM) 8 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos