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UCC21222
3.0kVrms 4A/6A dual-channel isolated gate driver with disable pin, programmable deadtime & 8V UVLO
Data sheet
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UCC21222
- Resistor-programmable dead time
- Universal: dual low-side, dual high-side or half-bridge driver
- 4A peak source, 6A peak sink output
- 3V to 5.5V input VCCI range
- Up to 18V VDD output drive supply
- 8V VDD UVLO
- Switching parameters:
- 28ns typical propagation delay
- 10ns minimum pulse width
- 5ns maximum delay matching
- 5.5ns maximum pulse-width distortion
- TTL and CMOS compatible inputs
- Integrated deglitch filter
- I/Os withstand –2V for 200ns
- Common-mode transient immunity (CMTI) greater than 100V/ns
- Isolation barrier life >40 Years
- Surge immunity up to 7800VPK
- Narrow body SOIC-16 (D) package
- Safety-related certifications (planned):
- 4242VPK isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
- 3000VRMS isolation for 1 minute per UL 1577
- CSA certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 end equipment standards
- CQC Certification per GB4943.1-2011
- Create a Custom Design Using the UCC21222 With the WEBENCH® Power Designer
The UCC21222 device is an isolated dual channel gate driver with programmable dead time. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.
The device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. A 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.
The input side is isolated from the two output drivers by a 3.0kVRMS isolation barrier, with a minimum of 100V/ns common-mode transient immunity (CMTI).
Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include a disable feature to shut down both outputs simultaneously when DIS is set high, an integrated deglitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection.
Technical documentation
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Evaluation board
UCC21220EVM-009 — UCC21220 4-A, 6-A 3.0-kVRMS Isolated Dual-Channel Gate Driver Evaluation Module
UCC21220EVM-009 is designed for evaluating UCC21220, which is a 3.0-kVRMS Isolated Dual-Channel Gate Driver with 4.0-A source and 6.0-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component selection (...)
User guide: PDF
Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs
PMP41006 — 1-kW reference design with CCM totem pole PFC and current-mode LLC realized by C2000™ and GaN
This reference design demonstrates a hybrid hysteresis control (HHC) method, a kind of current-mode control method on half-bridge LLC stage with a C2000™ F28004x microcontroller. The hardware is based on TIDA-010062, which is 1-kW, 80-Plus titanium, GaN CCM totem pole bridgeless PFC and half-bridge (...)
Test report: PDF
Reference designs
TIDA-010203 — 4-kW single-phase totem pole PFC reference design with C2000 and GaN
This reference design is a 4-kW CCM totem-pole PFC with F280049/F280025 control card and LMG342x EVM board. This design demos a robust PFC solution, which avoids isolated current sense by putting the controller's ground in the middle of a MOSFET leg. Benefitting from non-isolation, AC current (...)
Reference designs
PMP41043 — 1.6-kW reference design with CCM totem pole PFC and current-mode LLC realized by C2000 and GaN
This reference design demonstrates a hybrid hysteresis control (HHC) method, a current mode control method on half-bridge LLC stage with a C2000 F28004x microcontroller. The hardware is based on TIDA-010062 which is 1-kW, 80 Plus titanium, GaN CCM totem pole bridgeless PFC and half-bridge LLC (...)
Test report: PDF
Reference designs
PMP40500 — 54-VDC input, 12-V 42-A output half-bridge reference design
This 12-V, 42-A output half-bridge reference design is for bus converters in wired networking campus and branch switches. The design features high efficiency and various fault protections (over-current and short-circuit). The design provides an efficiency comparison using 3 kVRMS basic and (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
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